Peripheral Interfacing ICs

• I/O devices are of different functions and specifications.

• Microprocessor cannot manage them appropriately  needs
extra hardware to handle them.
• Various interfacing ICs designed  programmable.
1.Programmable Peripheral Interface
2.Programmable Interval Timer
3.Programmable Serial Communication Interface
4.Programmable Keyboard / Display Interface
1. Programmable Peripheral Interface (PPI-8255)
• Widely used, flexible, economical.
• Can be used with any Intel microprocessor.
• 24 bidirectional I/O lines  3 ports:
PORT A, PORT B, PORT C.
• Port A & Port B are 8-bit ports.
• Port C  used either as two 4-bit
ports (PCU , PCL) or 8 one-bit ports.
• Port A and PCU  Group A
• Port B and PCL  Group B
Block diagram of 8255
• IC8255 consists of two 8-bit ports (PA & PB), two 4-bit ports
(PCU & PCL), data bus buffer and control logic.
1. PORT A, B, C:
• Contains three ports (PA, PB and PC).
• Port A & Port B are 8-bit ports.
• Port C  used as two 4-bit ports (PCU , PCL) or eight 1-bit ports.
2. Group A & Group B control:
• Functionally, the ports are grouped under two sets  Group A &
Group B.
• Port A and PCU  Group A, Port B and PCL  Group B.
• Group control blocks receives control information and issues
commands to the associated ports.
3. Data Bus Buffer:
• 8-bit tri-state buffer to interface the chip to the s/m data bus.
• Data, control word and status information are transferred
through the data bus.
4. Read/Write Control:
• To control the internal operation.
• To control the transfer of data, control word or status words.
• Accepts inputs from address bus and control bus of µP  issues
command to other blocks.
a) CS (Chip Select):
• Low on this signal selects the PPI for communication with µP.
• Derived from the address bus using a logic circuit.
b) A1, A0 (Port Select):
• Select desired port or control register for writing / reading.
• Control register can only be written into  no reading.

 Note : Signals CS, A1 & A0 together decides the port

addresses.
Port Address
A 80H
B 81H
C 82H
Control Register 83H
c) RD (Read):
• Low on this input enables the read operation. i.e. data on the
selected port is read into CPU through data bus.
d) WR (Write):
• Low on this input enables the write operation. i.e. data is written
into the selected port or control register.

Functional Modes
• Basically two functional modes :
1. BSR mode  Bit Set Reset  for Port C only  can handle
each bit in PC individually.
2. I/O mode  all ports  modes of operation : mode 0,1,2.
Modes of operation
• Three modes of operation under I/O mode : Mode 0, 1 & 2.
a) Mode 0:
• All ports are simple input / output ports.
• Each port can be programmed to function as I/P or O/P.
• No handshake facility
b) Mode 1:
• Handshake mode.
• Port A & Port B are used as 8-bit i/p or o/p port.
• 3 bits of PCU & PCL are used as handshake signals for PA & PB
respectively.
• Remaining 1 bit each of PCU & PCL - simple I/O functions.
• Handshake signals (with PA / PB as input) are:

1) STB (strobe input)

• Signal from I/O device to indicate that data is sent.
2) IBF (input buffer full)
• Acknowledgement by PPI on obtaining STB to indicate that
the data is received.
3) INTR (interrupt request)
• Interrupt signal sent by PPI to µP on obtaining STB.
• µP immediately reads the data from the port of PPI.
• Handshake signals (with PA / PB as output) are:

1) OBF (output buffer full)

• Signal sent by PPI to peripheral device when a data byte is
received from µP.
• Data also transferred.
2) ACK (Acknowledgement)
• Sent by peripheral device on obtaining data byte.
3) INTR (interrupt request)
• Interrupt signal sent by PPI to µP to request for next data
byte.
c) Mode 2:
• Bidirectional communication with handshake.
• Applicable only to Port A.
• Mainly used for data transfer between two computers.
• Five bits of Port C are used for control signals (STB, IBF, INTR,
OBF, ACK).
• Port B may be programmed independently in mode 0 or 1.
• Remaining 3 bits of Port C may be used for simple I/O or
handshake of Port B.
Control word
• Control word is an 8-bit pattern written into the control register
to decide the port functions  i/p or o/p, mode etc.
• If D7 is 0  BSR mode ; if D7 is 1  I/O mode.

• BSR control
word pattern
• I/O mode control word pattern:
2. Programmable Interval Timer (PIT-8253)
• Generates accurate time delay.
• Applications include one shot generator, event counter, time
measurement between two events, RTC etc.
• IC8253  24 pin IC  maximum clock 2.6 MHz.
• Three 16-bit counters  six possible modes of operation.
• IC8254 is an upgraded version  pin compatible with 8253 
can operate with higher clock frequency  also count value
can be read back.
Block Diagram
• Includes 3 counters,
Read / write control
logic, data bus buffer
and control register.
1.Data Bus Buffer:
• 8-bit tri-state
bidirectional buffer to
interface the chip with
the µP data bus.
2.Control Word Register:
• Control word to specify
the counter to be used,
mode, etc.
3. Control logic:
• RD & WR are used for specifying read or write operation.
• Address lines A1 & A0  select counter / control register.
• CS  to select the chip via decoding circuitry.
4. Count registers
• 16-bit count value is loaded to the register of selected counter 
Decremented at each clock until reaches 0.
• CLK  to provide clock signal for counting.
• GATE  used to enable / disable the counter.
• OUT  used to indicate the end of counting.
Control word
Modes of operation
• IC8253 can operate in one of six possible modes.
1. Mode 0: Interrupt on terminal count
• OUT pin is low initially  count value loaded into the register 
counter decremented in each clock  OUT goes high when count
register reaches zero  this can be used as an interrupt.
2. Mode 1: Hardware-Retriggerable one-shot
• OUT is initially high  OUT goes low when GATE is triggered 
goes high again at the end of the count  thus creates a one-
shot pulse.
3. Mode 2: Rate generator
• To generate a pulse equal to the clock period.
• OUT stays high during counting until reaches 1  goes low for
one clock period  count value reloaded automatically  pulses
equal to one clock period are generated continuously.
4. Mode 3: Square wave generator
• OUT is high  count loaded  decremented by 2 for each clock
 when reaches zero, OUT goes low  count reloaded 
decremented by 2 for each clock  OUT is high  this process
repeated.
• Thus a continuous square wave with period equal to count is
generated.
5. Mode 4: Software-Triggered Strobe
• OUT is initially high  goes low for one clock at the end of the
count.
6. Mode 5: Hardware-Triggered Strobe
• Similar to mode4 except that it is triggered by the rising pulse of
the gate.
• OUT is low initially  count begins when gate is triggered  at
the end of the count, OUT goes low for one clock period.
3. Serial I/O concepts
• 8085 transfers 8-bit data over data bus  parallel mode.
• In serial mode, one bit data is transferred at a time over a
single line  parallel to serial conversion needed.
• Also, start bit and stop bit are required in asynchronous serial
communication.
• Implemented through software or programmable chips.
• In 8085, software controlled serial transmission is via the pins
SID & SOD  hardware approach is USART.
• IC8251 is a USART  programmable, widely used.
Programmable Communication Interface (8251)
• Designed for synchronous
and asynchronous serial
data communication.
• Control logic determines the
functions of the chip as per
control word.
• Modem control  to set up
data communication over
telephone lines.
• Data bus buffer interfaces
the chip with µP data bus.
Read / Write Control Logic:
• Consists of three buffer registers  control register for holding
control word, status register to indicate the ready status of the
peripheral, bi-directional data register for holding the data.
• There are six input signals to the control logic.
a) CS (Chip Select): to select 8251  connected to address bus
through a decoding circuitry.
b) C/D (control / data) when high, control or status register is
addressed  when low, data bus buffer is accessed.
c) WR (write): µP is going to write into the chip.
d) RD (read): µP is going to read from the chip.
e) RESET : To reset the chip.
f) CLK: the clock input  usually connected to system clock.
Transmitter section:
• Converts parallel data from µP into serial stream and
transmit via TxD line with appropriate framing bits.
Receiver section:
• Receives serial stream from peripheral device via RxD line,
removes framing bits, converts into parallel data and
transfers to µP.
4. Programmable Keyboard / Display Interface (8279)
• To interface matrix keyboard & multiplexed display.
• Relieves the processor from checking the keyboard and
refreshing the display.
• 40 pin IC  two segments  Keyboard, display.
• 64-key keyboard can be connected  keypresses are stored
in internal FIFO memory  interrupt generated with each
entry.
• 16 character displays can be connected  character codes
are stored in a 16 X 8 RAM.
Block diagram
• Four major sections : Keyboard, scan, display, µP interface.
Keyboard section:
• The eight lines (RL0 – RL7) are connected to eight columns of
keyboard.
• 8 X 8 FIFO RAM  8 registers of 8 bit size  stores keyboard
entries  interrupt request generated.
• Keys automatically debounced.
• Operate in two modes  2 Key lockout, N Key roll over
• 2 key lockout  if two keys are pressed simultaneously, only
first key is recognized.
• N key roll over  simultaneous keys are recognized.
Display section:
• Eight output lines in two groups  A0 – A3 & B0 – B3
• Output lines can be used either as a group of 8 lines or as two
groups of four to connect multiplexed display.
• Output lines are connected to 7 segment LEDs.
• Codes for characters to be displayed are stored in 16 X 8
display RAM.
• Display registers  holds bit pattern of character to be
displayed.
Scan section:
• Has a scan counter & 4 scan lines SL0 – SL3  row selection.
• Used for both keyboard section and display section.
• a) Decoded mode
 scan lines gives 4 values repeatedly  1110,1101,1011,0111.
 selects one of 4 rows in keyboard.
 can interface 4 X 8 keyboard / four 7 segment displays.
• b) Encoded mode
 scan lines give 4 bit count  decoded using external 4 to 16
decoder to generate 16 lines for scanning.
 selects one of the 8 rows of keyboard.
 can interface 8X8 keyboard / sixteen 7 segment displays.
µP interface section:
• Eight bidirectional data lines (DB0-DB7) connecting to Data bus.
• A0  Buffer address  0 for data & 1 for control word / status.
• IRQ  interrupt request  set when data exists in FIFO RAM.
• CLK  works with 100KHz.
• RESET  resetting the device.
• RD  to specify read operation.
• WR  to specify write operation.
• CS  to select the chip via decoding circuitry.
Keyboard interface working
• Scan lines helps to scan keyboard rows one by one  selected
row will have logic 0 at its input.
• If any key in that row is pressed, corresponding RL line
becomes logic low.
• Using row & column numbers, depressed key is identified 
ASCII code is stored in FIFO RAM.
• IRQ is generated  processor read the key code.
Display interface working
• Code for character to be displayed is stored in display RAM.
• Using scan lines, desired display is chosen
• Code is transferred to display the character.