ARM- Instruction Set – 2

& Pipelining
M3: Embedded Architectures- 1: RISC Architecture - ARM
Addressing Modes
• Mode 1: Shifter operands for data processing inst
• Mode 2: Load/Store word/unsigned byte
• Mode3: Load/Store half-word/signed byte

RL 3.2.3 Embedded System Design © K.R.Anupama &

• Mode4: Load/Store multiple
• Mode5: Load/Store co-processor

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x = (a+b)-c;
ADR r4,a
LDR r0,[r4]
ADR r4,b

RL 3.2.1 Embedded System Design © K.R.Anupama &

LDR r1,[r4]
ADD r3,r0,r1
ADR r4,c
LDR r2,[r4]
SUB r3,r3,r2

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ADR r4,x
STR r3,[r4]

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31-28 27 26 25 24 23 22 21 20 19-16 15-0

Cond 1 0 0 P U 0 W L Rn Reg List

LDM/STM {condn} <addr mode> Rn, <Reg List>

Examples
LDMIA R0, {R5 - R8}

RL 3.2.1 Embedded System Design © K.R.Anupama &

STMDA R1!, {R2, R5, R7 - R9, R11}
STMFD R13!, {R2-R9}
STMEA R13!, {R2-R9}

Addressing Mode – IA, IB, DA, DB, FD, FA, EA,ED

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0x204 20304050
0x200 21314151
0x1fc
0x1fc 22324252
22324252
0x1f8 23334353
0x1f8 23334353
0x1f4 24344454
0x1f4
0x1f0 25354555

RL 3.2.1 Embedded System Design © K.R.Anupama &

0x1f0
0x1ec
0x1ec
0x1e8
0x1e8
0x1e4
0x1e0
0x1e4

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0x1e0 Empty
Stack Fully Descending
Descending

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0x204
0x200
0x1fc
0x1fc
0x1f8
0x1f8
0x1f4
0x1f4
0x1f0 24344454
0x1f0

RL 3.2.1 Embedded System Design © K.R.Anupama &

0x1ec 23334353
0x1ec
0x1e8 22324252
0x1e8
0x1e4 22324252
21314151
0x1e0
0x1e4 20304050
21314151
0x1e0 Fully
Stack 20304050
Empty Ascending
Ascending

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Branch instructions
conditional branch forwards /backwards up to 32MB
branch /jump can also be generated by writing a value to R15

31-28 27 26 25 24 23-0

Cond 1 0 1 L 24- immediate value

RL 3.2.1 Embedded System Design © K.R.Anupama &

B/BL {condn} ,<Immediate Value>
Examples
B label
BCC label
BEQ label
MOV PC, #0
BL func

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MOV PC, LR
LDR PC, #func

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 Pipeline in ARM
• 3 stages of pipeline
• Fetch-Decode-Execute
• Normal Instruction require three clock cycles – inst exec

RL 3.2.1 Embedded System Design © K.R.Anupama &

latency
• 1 cycle/instruction does not hold good for all insts
• Multiple load instruction
• Several cycles during execution phase

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add r0,r1,r2 fetch decode execute
sub r2,r3,r6 fetch decode execute
cmp r2,r4 fetch decode execute

RL 3.2.1 Embedded System Design © K.R.Anupama &

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add r0, r1,r2 fetch decode execute
ldmia r0,{r1,r3} fetch decode execute execute
add r0,r2,r3 fetch decode
sub r0,r0,r7 fetch

Data stall

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 stall

bne nxt fetch decode execute execute execute

sub r2,r3,r6 fetch decode execute
sub r1,r2,r5 fetch decode
nxt: add r0,r2,#3
fetch decode execute

RL 3.2.1 Embedded System Design © K.R.Anupama &

2 holes

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bne nxt fetch decode execute
nop fetch decode execute
nop
fetch decode execute
sub r2,r3,r6
-----

RL 3.2.1 Embedded System Design © K.R.Anupama &

nxt: add r0,r2,#3 fetch decode execute

Delayed Branching

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