Digital Integrated Circuits

Week 3

Melik YAZICI
Silicon Ingot

• CZ ingot growth requires chunks of

polycrystalline silicon.
• To grow an ingot, the first step is to
heat the silicon to 1420°C, above
the melting point of silicon
Silicon Lattice
• Germanium (element 32) and silicon (element 14)
each have four valence electrons, which fill up the
valence band when these metals form a crystal.

• At temperatures close to 0K electrons in

outermost shell are tightly bound (insulator)

• At higher temps (around 300K), some electrons

have thermal energy to break covalent bonds

• Pure silicon has no free carriers and conducts

poorly.

Silicon covalent bond

Conductivity in Semiconductors
• Small amount of phosphorus is
added to silicon
• Phophorus atoms will substitute
silicon atom in the lattice Free electron

• The small amounts are carefully

controlled in the production
process and are only about
0.0001% of the total atoms.
• This process is called doping, and
the impurities are called dopants.
N type doping
PN Junction
CMOS
Introduction
Inverter Cross Section

• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors

36
 Introduction
Well and Substrate Taps

• Substrate must be tied to GND, n-well to VDD

• Metal to lightly-doped semiconductor forms poor connection called Schottky Diode
• Use heavily doped well and substrate contacts / taps

37
Introduction
Inverter Mask Set

• Transistors and wires are defined by masks

• Cross-section taken along dashed line

38
Introduction
Mask Views

39
Introduction
Fabrication Steps

40
Introduction
Oxidation

41
Introduction
Photoresist

42
Introduction
Lithography

43
Photolithography
• From Greek:
• photo – light
• lithos – stone
• graphe – picture
• “carving pictures in stone using light”
• Photomask (reticle):
• Chrome covered quartz glass.
• Photoresist: Wavelenght 193 nm
• Organic material, sensitive to light. Minimum Pitch
• Developer:
• Solvent that dissolves the unexposed
(exposed) photoresist.
Material constant ~0.8
Angle of acceptance
Refractive index (air=1)
(bigger=larger lens)
Photolithography
Resolution Enhancement Techniques:
• Use immersion (wet) lithography
(nwater=1.43)
• Use mask and layout techniques
• Use a smaller wavelength (193 nm).
• From 7nm (7+), EUV (13 nm) is used.

immersion (wet) lithography

Photoligtography
• Step and scan
Photoligtography
• Optical Proximity Corrections (OPC)
Introduction
Etch

44
Introduction
Strip Photoresist

45
Introduction
nWell

46
Introduction
Strip Oxide

47
Introduction
Polysilicon

48
Introduction
Polysilicon Patterning

49
Introduction
N diffusion

50
Introduction
N diffusion cont’d

51
Introduction
N diffusion cont’d

52
Introduction
P diffusion

53
Introduction
Contacts

54
Introduction
Metallization

55
Deep N-Well
• Can we change the body voltage of an nMOS transistor
• Triple Well Process
Introduction
Metal Layer Cross Section

56
Metal Layers (Backend)
• ILD = Inter-layer Dielectric (low-k)
• Passivation protects the final layer
• Al or Cu for Metal layers
• W for via
Antenna Effect
• Charge is built up on interconnect layers
• Plasma Etch
• If enough charge is created, this can cause a high voltage to breakdown
the thin gates.
Antenna Effect
• “Bridging” or “Antenna Diodes” are used to eliminate the
Antenna Effect.
Density
• Metal layers should have between ~30% to ~70% density.
• Maximum metal widths require slotting.
Latchup
• The multiple n-type and p-type regions in
the CMOS process create parasitic BJT
transistors.
• Unintentional “Thyristors” can turn on
and short VDD and GND.
• This requires power down at the least,
and
sometimes causes chip destruction.
• To reduce the risk of latchup,
distribute
well/substrate contacts across the
chip
Bulk Contacts
• To ensure a constant body voltage across large areas,
Bulk Contacts or Taps have to be added frequently.
Process Variations
Variation can occur at different levels:
• Fab to Fab variation
• Lot to Lot variation
• Wafer to Wafer variation
• Die to Die Variation
• Device to Device Variation
Process Parameters
• Such as impurity concentrations, oxide
thickness, diffusion depth.
• Caused during Deposition and Diffusion
steps.
• Affect VT and tox.
Device Dimensions Delay of Adder Circuit as a function of variations in L and
• Lengths and widths of gates, metals, etc. VT
• Caused due to photolithographic
limitations.
Types of Process Variation
Random Variation:
Occurs without regards to the location and patterns of the transistors within the
chip (e.g., RDF)
• For example – Random Dopant Fluctuation (RDF)
Systematic Variation:
Related to the location and patterns
• For example – layout density, well-proximity, distance from center of wafer
Intra-die (Within-die) Variations
Variations between elements in the same chip
• A.k.a. – “Local Variation”
Inter-die (Die-to-Die)
Variations between chips in the same wafer or in different wafers
• A.k.a. – “Global Variation”
Random Doping Fluctuation (RDF)
• The most significant factor in
variations of the threshold voltage is
due to the number and location of
dopant atoms in the channel.
• In 1μm technology,
there were many thousands of dopants.
• In 32 nm technology,
there are less than 100 dopants!

RDF accounts for about 60% of the

threshold
variation.
Managing Process Variation in Intel’s 45nm CMOS Technology,
Intel Technology Journal, Volume 12, Issue 2, 2008
Line Edge/Width Roughness (LER/LWR)
• Line Edge Roughness (LER) and
Line Width Roughness (LWR)
cause changes in sub-threshold
current and threshold voltage.
• These problems are expected to
surpass RDF as the main cause
of variations at deep nanoscale
technologies.
Additional Variations
Gate Dielectric Variation
• Oxide Thickness
• Fixed Charge
• Defects and Traps
CMP Variations
• Metal Gate height
• ILD (Insulation Layer Dielectric) and Interconnect Thickness
Strain Variation
Implant Variation
Rapid Thermal Anneal (RTA) Variation
Impact of Process Variations