Design methodologies

• A procedure for designing a system.

• Understanding your methodology helps you ensure you didn’t skip
anything.
• Compilers, software engineering tools, computer-aided design (CAD) tools,
etc., can be used to:
help automate methodology steps;
keep track of the methodology itself.

18MHC205J - Microcontrollers and Embedded System 1

 Design goals

• Performance.
Overall speed, deadlines.
• Functionality and user interface.
• Manufacturing cost.
• Power consumption.
• Other requirements (physical size, etc.)

18MHC205J - Microcontrollers and Embedded System 2

Levels of abstraction

18MHC205J - Microcontrollers and Embedded System 3

 Top-down Vs bottom-up

• Top-down design:
start from most abstract description;
work to most detailed.
• Bottom-up design:
work from small components to big system.
• Real design uses both techniques.

18MHC205J - Microcontrollers and Embedded System 4

 Stepwise refinement

• At each level of abstraction, we must:

analyze the design to determine characteristics of the current state of the
design.
refine the design to add detail.

18MHC205J - Microcontrollers and Embedded System 5

 Design Technology
• The manner in which we convert our concept of desired system functionality
into an implementation

18MHC205J MICROCONTROLLERS N EMBEDDED SYSTEMS 6

 Automation: synthesis
• The parallel evolution of compilation and synthesis
• Synthesis levels
• Logic synthesis
– Two-level logic minimization
– Multi-level logic minimization
– FSM synthesis
– Technology mapping
• Register-transfer synthesis
• Behavioral synthesis
• System synthesis and hardware/software co-design

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 Design productivity exponential increase

• Exponential increase over the past few decades

18MHC205J MICROCONTROLLERS N EMBEDDED SYSTEMS 8

 Independence of Processor and IC technologies
• Basic tradeoff
– General vs. custom
– With respect to processor technology or IC technology
– The two technologies are independent
General-purpose Single-
processor ASIP purpose
General, processor Customized,
providing improved: providing improved:

Flexibility Power efficiency

Maintainability Performance
NRE cost Size
Time- to-prototype Cost (high volume)
Time-to-market
Cost (low volume)

PLD Semi-custom Full-custom

18MHC205J MICROCONTROLLERS N EMBEDDED SYSTEMS 9

 Design productivity gap
• While designer productivity has grown at an impressive rate over the past decades, the rate of
improvement has not kept pace with chip capacity

10,000 100,000

1,000 10,000

Logic transistors per chip 100 1000

(in millions) 10 Gap 100 Productivity
IC capacity (K) Trans./Staff-Mo.
1 10

0.1 1
productivity
0.01 0.1

0.001 0.01
1981

1983

1985

1989

1991

1993

1995

1999

2001

2003

2009
1987

1997

2005

2007
1981 leading edge chip required 100 designer months
10,000 transistors (ie., 100 transistors/month)
2002 leading edge chip requires 30,000 designer months
150,000,000 (ie., 5000 transistors/month)
Designer cost increase from $1M to $300M
18MHC205J MICROCONTROLLERS N EMBEDDED SYSTEMS 10
 The mythical man-month
• The situation is even worse than the productivity gap indicates
• In theory, adding designers to team reduces project completion time
• In reality, productivity per designer decreases due to complexities of team management and communication
• In the software community, known as “the mythical man-month” (Brooks 1975)
• At some point, can actually lengthen project completion time! (“Too many cooks”)

Team
• 60000 15
1M transistors, 1 designer=5000 trans/month 16 16
• 50000 18
Each additional designer reduces for 100 19
trans/month 40000
24 23
• So 2 designers produce 4900 trans/month each
30000
Months until completion
20000 43
10000 Individual

0 10 20 30 40
Number of designers

18MHC205J MICROCONTROLLERS N EMBEDDED SYSTEMS 11

 Introduction
System Design Goals

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 Introduction

• What does “Design” means?

Task of defining system functionality and converting that functionality into physical
implementation.
Convert functionality to physical implementation while
• Satisfying constrained metrics
• Optimizing other design metrics

• Designing embedded systems is hard because of

– Complex functionality
• Millions of possible environment scenarios. Ex: Elevator Controller.
• So many Competing, tightly constrained metrics.
– Productivity gap
• As low as 10 lines of code or 100 transistors produced per day
Many possible combinations of buttons being pressed.
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 Improving productivity

Design technologies developed to improve productivity, we focus on technologies

advancing hardware / software view:
 Automation: Synthesis
 Computer program to replace manual design.
 Which made Hardware design look like Software design.
 Reuse
 Process of using predesigned components.
 Core in the Hardware domain.
 Verification
 Task of ensuring correctness/completeness of each design step.
Specification
 Hardware/Software co-simulation. Automation

Verification Reuse
Implementation

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 The parallel evolution of compilation and synthesis

• In the early design was mostly hardware,

The co-design ladder
software was fairly simple.
• Software complexity increased with advent Sequential program code (e.g., C, VHDL)
of general-purpose processor.
Behavioral synthesis
• Different techniques for software design Compilers
(1990s)

and hardware design: (1960s,1970s)

Register transfers
– Caused division of the two fields RT synthesis
Assembly instructions (1980s, 1990s)
• Hardware/software design fields rejoining
Logic equations / FSM's
– Both can start from behavioral description in Assemblers, linkers
Logic synthesis
sequential program model (1950s, 1960s)
(1970s, 1980s)

Machine instructions Logic gates

Microprocessor plus Implementation VLSI, ASIC, or PLD

program bits implementation

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 Cont.
 Software design evolution
 Machine instructions The co-design ladder
 Collection machine instructions called Program (0’s,
1’s). Sequential program code (e.g., C, VHDL)

 Assemblers
 Convert assembly programs into machine Behavioral synthesis
(1990s)
instructions, due to hard dealing with huge number Compilers
of 0’s, 1’s. (1960s,1970s)
 Compilers Register transfers

 translate sequential programs into assembly RT synthesis

 Hardware design evolution Assembly instructions (1980s, 1990s)

 Interconnected logic gates

Logic equations / FSM's
 Logic synthesis Assemblers, linkers
 converts logic equations or FSMs into gates (1950s, 1960s) Logic synthesis
(1970s, 1980s)
 Register-transfer (RT) synthesis
 converts FSMDs into FSMs, logic equations,
Machine instructions Logic gates
predesigned RT components (registers, adders, etc.)
 Behavioral synthesis Microprocessor plus Implementation VLSI, ASIC, or PLD
 converts sequential programs into FSMDs program bits implementation

Hardware design involves many more dimensions, while compilers must generate assembly instructions to implement itself. 16
Hardware Designer concerned about size, power, performance and other metrics.
 Synthesis Levels

Gajski’s Y-chart Carry-ripple adder Addition

 Each axis represents type of description Structural Behavior
 Behavioral
Processors, memories Sequential programs
 Defines outputs as function of inputs
 Structural Registers, FUs, MUXs Register transfers

 Implements behavior by connecting Gates, flip-flops Logic equations/FSM

components with known behavior
 Physical Transistors Transfer functions

 Gives size/locations of components and wires

on chip/board Cell Layout
 Synthesis converts behavior at given level to Modules
structure at same level or lower Chips
 E.g.,
Boards
 FSM → gates, flip-flops (same level)
 FSM → transistors (lower level) Physical
 FSM X registers, FUs (higher level)
 FSM X processors, memories (higher level)

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 Logic Synthesis
• Converting logic-level behavior to structural implementation
By converting Logic equations and/or FSM to connected gates.

• Combinational logic synthesis

– Two-level minimization
– Multilevel minimization

• FSM synthesis
– State minimization
– State encoding

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 Two-level minimization
• Represent logic function as sum of products (or product of sums)
– AND gate for each product
– OR gate for each sum
Sum of products
• This minimization gives best possible performance F = abc'd' + a'b'cd + a'bcd + ab'cd

when at most we have 2 gates delay Direct implementation

• Goal: minimize size a
– Minimum cover b
– Minimum cover that is prime c F
d

4 4-input AND gates and

1 4-input OR gate
→ 40 transistors

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 Minimum Cover

 Minimum # of AND gates (sum of products)

 Literal: variable or its complement
 a or a’, b or b’, etc.
 Minterm: product of literals
 Each literal appears exactly once
 abc’d’, ab’cd, a’bcd, etc.
 Implicant: product of literals
 Each literal appears no more than once
 abc’d’, a’cd, etc.
 Covers 1 or more minterms
 a’cd covers a’bcd and a’b’cd
 Cover: set of implicants that covers all minterms of function
 Minimum cover: cover with minimum # of implicants

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 Cont.
Minimum cover: K-map approach
K-map: sum of products K-map: minimum cover
cd00 cd00
Karnaugh map (K-map) ab
00 0
01

0
11

1
10

0
ab
00 0
01

0
11

1
10

0
 1 represents minterm 01 0 0 1 0 01 0 0 1 0
11 1 0 0 0 11 1 0 0 0
 Circle represents implicant 10 0 0 1 0 10 0 0 1 0

Minimum cover Minimum cover

F=abc'd' + a'cd + ab'cd
 Covering all 1’s with min # of circles
Minimum cover implementation
 Example: direct vs. min cover a
 Less gates b 2 4-input AND gate
c F 1 3-input AND gates
4 vs. 5 1 4 input OR gate
→ 28 transistors
 Less transistors d
28 vs. 40

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 Minimum cover that is prime

Minimum # of inputs to AND gates

Prime implicant K-map: minimum cover that is prime
cd
ab
 Implicant not covered by any other implicant 00 01 11 10
00 0 0 1 0
 Max-sized circle in K-map 01 0 0 1 0
11 1 0 0 0
Minimum cover that is prime 10 0 0 1 0

 Covering with min # of prime implicants Minimum cover that is prime

 Min # of max-sized circles F=abc'd' + a'cd + b'cd

 Example: prime cover vs. min cover Implementation

 Same # of gates a 1 4-input AND gate
b 2 3-input AND gates
4 vs. 4 c F 1 4 input OR gate
 Less transistors → 26 transistors
d
26 vs. 28

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 Minimum cover: heuristics

• K-maps give optimal solution every time

– Functions with > 6 inputs too complicated
– Use computer-based tabular method
• Finds all prime implicants
• Finds min cover that is prime
• Also optimal solution every time
• Problem: 2n minterms for n inputs
– 32 inputs = 4 billion minterms
– Exponential complexity

• Heuristic
– Solution technique where optimal solution not guaranteed
– Hopefully comes close

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 Heuristics: iterative improvement
• Start with initial solution
– i.e., original logic equation
• Repeatedly make modifications toward better solution
• Common modifications
– Expand
• Replace each nonprime implicant with a prime implicant covering it
• Delete all implicants covered by new prime implicant
– Reduce
• Opposite of expand
– Reshape
• Expands one implicant while reducing another
• Maintains total # of implicants
– Irredundant
• Selects min # of implicants that cover from existing implicants
• Synthesis tools differ in modifications used and the order they are used

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 Multilevel logic minimization

• Trade performance for size

– Increase delay for lower # of gates
– Gray area represents all possible solutions
– Circle with X represents ideal solution
.
• Generally not possible in
im
lm
– 2-level gives best performance ti - l eve
ul

delay
m
• max delay = 2 gates
• Solve for smallest size
– Multilevel gives pareto-optimal solution 2-level minim.
• Minimum delay for a given size size
• Minimum size for a given delay

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 Example
 Minimized 2-level logic function:
 F = adef + bdef + cdef + gh 2-level minimized
 Requires 5 gates with 18 total gate inputs a
 4 ANDS and 1 OR d
b
 After algebraic manipulation: e
 F = (a + b + c)def + gh c F
 Requires only 4 gates with 11 total gate inputs f
 2 ANDS and 2 ORs g
 Less inputs per gate h
 Assume gate inputs = 2 transistors
 Reduced by 14 transistors multilevel minimized
 36 (18 * 2) down to 22 (11 * 2) a
b
 Sacrifices performance for size c
 Inputs a, b, and c now have 3-gate delay d
e
 Iterative improvement heuristic commonly used f
F
g
h

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 Summary
• Design technology seeks to reduce gap between IC capacity growth and
designer productivity growth
• Synthesis has changed digital design
• Increased IC capacity means sw/hw components coexist on one chip
• Design paradigm shift to core-based design
• Simulation essential but hard
• Spiral design process is popular

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