Unit-7: I/O Interfacing: (MPI) GTU # 3160712

Microprocessor and Interfacing
(MPI)
GTU # 3160712
Unit-7:
I/O Interfacing
Positive Vibes:MPI is the interesting, easiest and scoring subject.
Prof. Swati R Sharma

Computer Engineering Department
Darshan Institute of Engineering & Technology, Rajkot
swati.sharma@darshan.ac.in
(O) 9727747317
Subject Overview
Sr. No. Unit % Weightage

1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 12%
4 Assembly Language Programming Basics 13%
5 8085 Assembly Language Programs 12%
6 Stack & Subroutines 13%
7 I/O Interfacing 20%
8 Advanced Microprocessors 15%
Prof. Swati R Sharma Unit 7 – I/O Interfacing 2

 Topics
Loopingto be covered
 Introduction to Interfacing Concepts

 I/O Ports
 Interfacing Of I/O Devices
 Interrupts In 8085
 Programmable Interrupt Controller 8259A
 Programmable Peripheral Interface 8255A
Introduction to Interfacing
Concepts
Introduction to Interfacing Concepts
 Interface is the path for communication between two components. Positive Vibes:MPI is the interesting, easiest and scoring subject.
 Interfacing is of two types, memory interfacing and I/O interfacing.
IO Interfacing
What do you mean by I/O Interfacing?
 There are various communication devices like the keyboard, mouse, printer, etc.
 So, we need to interface the keyboard and other devices with the microprocessor by using
latches and buffers.
 This type of interfacing is known as I/O interfacing.

8085 Interfacing Pins
Following is the list of 8085 pins used for interfacing with Positive Vibes:MPI is the interesting, easiest and scoring subject.
other devices:
1. A15-A8 (Higher Address Bus)
2. AD7-AD0(Lower Address/Data Bus)
3. ALE
4. RD
5. WR
6. READY

Ways of Communication with Microprocessor
There are two ways of communication in which the microprocessor can connect with the outside
world.
1. Serial Communication Interface
In this type of communication, the interface gets a single bit of data from the microprocessor
and sends it bit by bit to the other system serially and vice-a-versa.
2. Parallel Communication Interface

In this type of communication, the interface gets a byte of data from the microprocessor and
sends it bit by bit to the other systems in simultaneous (or) parallel fashion and vice-a-versa.

Types of I/O
Peripheral I/O Memory Mapped I/O
Here Peripheral is identified with an 8-bit address. Here Memory Mapped I/O is identified with a 16-
bit address.
Instructions IN and OUT are used to implement Data transfer is implemented by using memory
data transfer between Microprocessor and related instructions, such as STA, STAX, LDA,
Peripherals. LDAX, MOV etc.

Interrupts in 8085
Interrupts in 8085
An Interrupt is a process where an external device can get the attention of the microprocessor.
 The process starts from the I/O device

 The process is asynchronous.
 An interrupt is considered to be an emergency signal that may be serviced.
 The Microprocessor may respond to it as soon as possible.
What happens when Microprocessor is interrupted ?
 When the Microprocessor receives an interrupt signal, it suspends the currently executing
program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt.
 Each interrupt will most probably have its own ISR.
Responding to Interrupts
 Responding to an interrupt may be immediate or delayed depending on whether the interrupt is
maskable or non-maskable.
Interrupts in 8085
 Interrupts are the signals generated by the external Positive Vibes:MPI is the interesting, easiest and scoring subject.
devices to request the microprocessor to perform a

task.
 There are 5 interrupt signals as follows:
1. TRAP
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR

Interrupts in 8085
The 8085 has 5 interrupt inputs Positive Vibes:MPI is the interesting, easiest and scoring subject.
 The INTR input.

 The INTR input is the only non-vectored interrupt.
 INTR is maskable using the EI/DI instruction pair. Interrupt Maskable Vectored
 RST 5.5, RST 6.5, RST 7.5 are all automatically INTR Yes No
vectored. RST 5.5 Yes Yes

 RST 5.5, RST 6.5, and RST 7.5 are all maskable. RST 6.5 Yes Yes
 TRAP is the only non-maskable interrupt in the RST 7.5 Yes Yes
8085 TRAP No Yes
 TRAP is also automatically vectored

Classification of Interrupts
 Vector interrupt: Positive Vibes:MPI is the interesting, easiest and scoring subject.
 In this type of interrupt, the interrupt address is known to the processor.

 For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt:
 In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to
be sent externally by the device to perform interrupts.
 For example: INTR
 Maskable interrupt:
 In this type of interrupt, we can disable the interrupt by writing some instructions into the program.
 For example: RST7.5, RST6.5, RST5.5
 Non-Maskable interrupt:
 In this type of interrupt, we cannot disable the interrupt.
 For example: TRAP

 Software Interrupt: Positive Vibes:MPI is the interesting, easiest and scoring subject.
 In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt.
There are 8 software interrupts in 8085
 For example: RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware Interrupt:
 There are 5 interrupt pins in 8085 used as hardware interrupts.
 For example: TRAP, RST7.5, RST6.5, RST5.5,INTR

Interrupt Service Routine (ISR)

Interrupt Service Routine (ISR)
Definition Positive Vibes:MPI is the interesting, easiest and scoring subject.
A small program or a routine that when executed, services the corresponding interrupting source is
called an ISR.
 When a device interrupts, it actually wants the Microprocessor to give a service which is
equivalent to asking the Microprocessor to call a subroutine.
 This subroutine is called ISR (Interrupt Service Routine)
 The ‘EI’ instruction is a one byte instruction and is used to Enable the non-maskable interrupts.
 The ‘DI’ instruction is a one byte instruction and is used to Disable the non-maskable interrupts.

Programmable Peripheral
Interface 8255A
Programmable Peripheral Interface 8255A
 The 8255A is a general purpose programmable, parallel I/O device. Positive Vibes:MPI is the interesting, easiest and scoring subject.
 It is designed to transfer the data from simple I/O to interrupt I/O under certain conditions as
required.
 It can be used with almost any microprocessor.
 It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be configured as per the
requirement.
 It is flexible, versatile and economical but somewhat complex.
 The intent is to provide complete I/O interface in single chip.
 This chip directly interfaces to data bus of the processor.

8255A I/O port
PORT A 8-bit
GROUP A
CU 4-bit
8255A CL 4-bit
PORT C I/O Devices
GROUP B
PORT B 8-bit

8255A I/O port
8255A has three ports, i.e., PORT A, PORT B, and PORT C. Positive Vibes:MPI is the interesting, easiest and scoring subject.
 Port A contains 8-bit I/O latch/buffer.

 Port B is similar to PORT A.
 Port C splits into two parts, i.e. PORT C lower (PC3-
PC0) and PORT C upper (PC7-PC4) by the control word.
 These three ports are further divided into two groups,
 Group A includes PORT A and upper 4-bit of PORT C.
 Group B includes PORT B and lower 4-bit of PORT C.
These two groups can be programmed in three different
modes, i.e. the first mode is named as mode 0, the
second mode is named as Mode 1 and the third mode is
named as Mode 2.

Power +5V
Group A I/O
Suppliers GND Group A
Port A PA7-PA0
Control Positive Vibes:MPI is the interesting, easiest and scoring subject.
Bidirectional
Block diagram : 8255A
Data
bus
Data Bus Group A
D0-D7
Port C I/O
Buffer PC7-PC4
Upper
8-bit Internal data bus
RD Group B I/O
WR Port C PC3-PC0
A1 Read Lower
A0 Write Group B
Control Control
RESET
Logic I/O
Group B
PB7-PB0
Port B
CS
8255A Architecture: Control Logic
RD
WR
RD (READ) This is an active low signal, that enables Read operation. When A1 Read
signal is low MPU reads data from selected I/O port of 8255A A0 Write
WR (WRITE) This is an active low signal, that enables Write operation. When RESET Control
signal is low MPU writes data into selected I/O port or control Logic
register
RESET This is an active high signal, used to reset the device. That
means clear control registers. CS
CS This is Active Low signal.
(Chip Select) When it is low, then data is transfer to/from 8085.
CS signal is the master Chip Select.
A0 and A1 specify one of the I/O ports or control register

8255A Architecture: Chip Select
CS A1 A0 Selected
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 Control Register
1 X X 8255A is not selected

8255A Operating Modes
8255A has three different operating modes: Positive Vibes:MPI is the interesting, easiest and scoring subject.
1. Mode 0
2. Mode 1
3. Mode 2

8255A I/O ports and modes
D7 D6 D5 D4 D3 D2 D1 D0
0  BSR Mode 1  I/O Mode

For Port C
No effect on
I/O mode Mode 0 Mode 1 Mode 2
Simple I/O Handshake I/O Bidirectional

For ports A,B & C For ports A Databus for
and/or Port B Port A
Port C: bits are Port B:either

used for Mode 0/1
Handshake Port C: bits are
used for
Handshake.

Mode 0 Positive Vibes:MPI is the interesting, easiest and scoring subject.
 Simple I/O for port A,B and C

 In this mode, Port A and B is used as two 8-bit
ports and Port C as two 4-bit ports.
 Each port can be programmed in either input
mode or output mode.
 Ports do not have handshake or interrupt
capability.

Mode 1: Input or Output with Handshake Positive Vibes:MPI is the interesting, easiest and scoring subject.
 Handshake signal are exchanged between MPU

and peripheral prior to data transfer.
 In this mode, Port A and B are used as 8-bit I/O
ports.
 Mode 1 is a handshake Mode whereby ports A
and/or B use bits from port C as handshake
signals.
 In handshake mode, 2 types of I/O data transfer
can be implemented: status check and interrupt.

Mode 2 Positive Vibes:MPI is the interesting, easiest and scoring subject.
 In this mode, Port A can be configured as the

bidirectional port and Port B either in Mode 0 or
Mode 1.
 Port A uses 5 signals from Port C as handshake
signals for data transfer.
 The remaining three signals from Port C can be used
either as simple I/O or as handshake for port B.

Features of 8255A
The prominent features of 8255A are as follows: Positive Vibes:MPI is the interesting, easiest and scoring subject.
 It consists of three 8-bit IO ports i.e. PA, PB, and PC.

 Address/data bus must be externally demultiplexed.
 It has improved DC driving capability.

8255A: Control Register

8255A: Control Register
RD
WR Positive Vibes:MPI is the interesting, easiest and scoring subject.
WR
PORT A
Content of this 00 EN
register is known RD
as Control Word Control WR
Register
PORT C_U
CS
EN PORT C_L
10 EN
RD
WR
11
A1 Internal 10 PORT C
A0 Decoding 01
PORT B PORT B
00
PORT A EN
01

8255A: Control Word

8255A: Control Word
D7 D6 D5 D4 D3 D2 D1 D0 Positive Vibes:MPI is the interesting, easiest and scoring subject.
GROUP A GROUP B
PORT Cu(PC7-PC4) PORT CL(PC3-PC0)
1= Input 1= Input
0= Output 0= Output
PORT A PORT B
1= Input 1= Input
0= Output 0= Output
Mode Selection Mode Selection
00 = Mode 0 1= Mode 1
01 = Mode 1 0= Mode 0
1= I/O Mode 1X = Mode 2
0= BSR Mode

8255A: Control Word
 Accessed to write a control word when A0 Positive Vibes:MPI is the interesting, easiest and scoring subject.
and A1 are at logic1.

To communicate with peripherals through the
8255A, three steps are necessary:
1. Determine the addresses of ports A, B, and
C and of the control register according to
the Chip select logic and address lines A0
and A1.
2. Write a control word in the control register.
3. Write I/O instructions to communicate with
peripherals through ports A, B, and C

8255A: Control Word
Write an control word to identify mode 0 Positive Vibes:MPI is the interesting, easiest and scoring subject.
 Configure Port A and Port CU as output ports and Port B and CL as input ports.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 1 1
1= I/O Mode PORTACu(PCMode

PORT 7-PC4)Selection
PORT CL(PC3-PC0)
0= BSR Mode Mode Selection 1= Input
1= Input 1= Mode 1 1= Input
0= Output
0= Output 0= Mode 0 0= Output
00 = Mode 0
01 = Mode 1 PORT B
1X = Mode 2 1= Input
0= Output

8255A: Control Word
Write a control word to identify mode 0 Positive Vibes:MPI is the interesting, easiest and scoring subject.
 Configure Port A and Port CU as output

ports and Port B and CL as input ports.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 1 1
Control Word = 83 H

8255A: Control Word

8255A: Control Word Example
Write a program to read control word from Port B, display at Port A and read upper 4-bit from
Port C.
1. MVI A,D3H ;Load accumulator with controlword (1110 0011)

2. OUT 83H ;Write word in control register
3. IN 81H ;read switches at Port B
4. OUT 80H ;Display the reading at Port A
5. IN 82H ; Read at Port C
6. ANI F0H ; Mask lower 4-bit

8255A: BSR(Bit Set/Reset) Mode
D7 D6 D5 D4 D3 D2 D1 D0
0 X X X Bit Select S/R
BSR Mode 1= Set

0 = Reset
Not used, 000 PC0
Generally Set = 0 001 PC1
010 PC2
011 PC3
100 PC4
101 PC5
110 PC6
111 PC7
8255A: BSR(Bit Set/Reset) Mode
 In this mode any of the 8-bits of port C Positive Vibes:MPI is the interesting, easiest and scoring subject.
can be set or reset depending on D0 of

the control word.
 The bit to be set or reset is selected by
bit select flags D3, D2 and D1 of the
CWR(Control Word Register).
 BSR Control Word affects one bit at a
time.
 Does not affect the I/O mode.

Programmable Interrupt
Controller 8259A
Programmable Interrupt Controller 8259A: Introduction
 The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for use with the 8085 and
8086 microprocessors.
 The 8085 has only five number of hardware interrupts: TRAP,RST 7.5,RST 6.5,RST 5.5 and INTR.
 The 8259 can be used for applications that use more than five numbers of interrupts from
multiple sources.

Features :8259A
The main features of 8259 are listed below Positive Vibes:MPI is the interesting, easiest and scoring subject.
 Manage eight levels of interrupts.

 Eight interrupts are spaced at the interval of four or eight locations.
 Resolve eight levels of priority in fully nested mode, automatic rotation mode or specific
rotation mode.
 Mask each interrupt individually.
 Read the status of pending interrupt, in-service interrupt, and masked interrupt.
 Accept either the level triggered or edge triggered interrupt.

8259 Internal Block Diagram

8259 Internal Block Diagram INTA INT
D7-D0 CONTROL LOGIC Positive Vibes:MPI is the interesting, easiest and scoring subject.
DATA BUS
I
BUFFER
N
T
E
R
RD N
READ/WRITE A
WR IR0
LOGIC L
A0 IR1
INTERRUPT IR2
CS B IN-SERVICE IR3
PRIORITY REQUEST
U REGISTER IR4
CAS 0 RESOLVER REGISTER
CASCADE S (ISR) IR5
CAS 1 (IRR)
BUFFER/ IR6
CAS2 IR7
COMPARATOR
SP/EN
INTERRUPT MASK REGISTER
(IMR)
Read/Write Logic Positive Vibes:MPI is the interesting, easiest and scoring subject.
 When address line A0 is at logic 0, the

controller is selected to write a
command word or read status.
 The Chip Select logic and A0 determine
the port address of controller.
Control Logic
 It has two pins: INT as output and INTA
as input.
 The INT is connected to INTR pin of
MPU.

Interrupt Registers and Priority Resolver Positive Vibes:MPI is the interesting, easiest and scoring subject.
1. Interrupt Request Register (IRR)

2. Interrupt In-Service Register (ISR)
3. Priority Resolver
4. Interrupt Mask Register (IMR)
Interrupt Request Register (IRR) and Interrupt
In-Service Register (ISR)
 Interrupt input lines are handled by two
registers in cascade – IRR and ISR
 IRR is used to store all interrupt which are
requesting service.
 ISR is used to store all interrupts which are
being serviced.

Priority Resolver Positive Vibes:MPI is the interesting, easiest and scoring subject.
 This logic block determines the priorities of the

bit set in IRR.
 IR0 is having highest priority, IR7 is having
lowest priority.
Interrupt Mask Register
 It stores bits which mask the interrupt lines to
be masked.
 IMR operates on the IRR.
 Masking of high priority input will not affect the
interrupt request lines.

Cascade Buffer / Comparator Positive Vibes:MPI is the interesting, easiest and scoring subject.
 This block is used to expand the number of

interrupt levels by cascading two or more
8259As.

8259 Internal Block Diagram INTA INT
D7-D0 CONTROL LOGIC Positive Vibes:MPI is the interesting, easiest and scoring subject.
DATA BUS
I
BUFFER
N
T
E
R
RD N
READ/WRITE A
WR IR0
LOGIC L
A0 IR1
INTERRUPT IR2
CS B IN-SERVICE IR3
PRIORITY REQUEST
U REGISTER IR4
CAS 0 RESOLVER REGISTER
CASCADE S (ISR) IR5
CAS 1 (IRR)
BUFFER/ IR6
CAS2 IR7
COMPARATOR
SP/EN
INTERRUPT MASK REGISTER
(IMR)
Interfacing with Seven Segment

Display:LED
Interfacing with Seven Segment Display: LED
 Interface the 8085 Microprocessor System with seven segment display Positive Vibes:MPI is the interesting, easiest and scoring subject. a
through its programmable I/O port 8255.
f b
 Seven segment displays is often used in the digital electronic equipment g
to display information regarding certain process. e c
 I/O devices (or peripherals) such as LEDs and keyboards are essential
d
components of the microprocessor-based or microcontroller-based
systems.
 Classified into two groups
1. input devices
2. output devices
 Seven-segment LEDs Often used to display BCD numbers (1 through 9)
and a few alphabets.
 Each LED is called a segment and labeled as ‘a’ through ‘g’.

Interfacing 7 Segment LEDs as an Output
 Commonly used output peripherals in embedded systems are Positive Vibes:MPI is the interesting, easiest and scoring subject.
LEDs, seven-segment LEDs, and LCDs; the simplest is LED

Two ways of connecting LEDs to I/O ports:
1. LED cathodes are grounded and logic 1 from the I/O port turns on the LEDs - The current is
supplied by the I/O port called current sourcing.
2. LED anodes are connected to the power supply and logic 0 from the I/O port turns on the
LEDs - The current is received by the chip called current sinking.

Seven Segment LED: Example
LED a b c d e f g Hex Code

1 1 0 1 1 0 1 0X6D=2
1 1 1 1 1 1 0 0X7E=0
1 1 1 1 1 1 1 0X7F=8

GTU Exam Questions
Sr. Questions Marks
Positive Vibes:MPI is the interesting, easiest and scoring subject. Year
1. What is an interrupt? Explain various interrupts of the 8085 microprocessor. 4 W’17
W’18
W’19
2. Draw and explain the block diagram of the programmable interrupt controller(8259A). 7 W’17
S’18
W’18
S’19
3. Draw and explain the block diagram of the programmable peripheral interface (8255A). 7 W’17
S’19
4. How many I/O modes are available in 8255A programmable peripheral interface? List and explain them in 3 S’18
short.
5. Explain hardware and software interrupt. 3 S’18
S’19

References
Book: Microprocessor Architecture, Programming, and Applications with the 8085, Ramesh
Positive Vibes:MPI S. easiest and scoring subject.
is the interesting,
Gaonkar Pub: Penram International

Thank You

Unit-7: I/O Interfacing: (MPI) GTU # 3160712

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Microprocessor and Interfacing

Prof. Swati R Sharma

Sr. No. Unit % Weightage

Prof. Swati R Sharma Unit 7 – I/O Interfacing 2

 Introduction to Interfacing Concepts

 Interfacing is of two types, memory interfacing and I/O interfacing.

Prof. Swati R Sharma Unit 7 – I/O Interfacing 5

Prof. Swati R Sharma Unit 7 – I/O Interfacing 6

2. Parallel Communication Interface

Prof. Swati R Sharma Unit 7 – I/O Interfacing 7

Peripheral I/O Memory Mapped I/O

Prof. Swati R Sharma Unit 7 – I/O Interfacing 8

 The process starts from the I/O device

devices to request the microprocessor to perform a

Prof. Swati R Sharma Unit 7 – I/O Interfacing 11

 The INTR input.

vectored. RST 5.5 Yes Yes

Prof. Swati R Sharma Unit 7 – I/O Interfacing 12

 In this type of interrupt, the interrupt address is known to the processor.

Prof. Swati R Sharma Unit 7 – I/O Interfacing 14

Prof. Swati R Sharma Unit 7 – I/O Interfacing 15

Interrupt Service Routine (ISR)

Prof. Swati R Sharma Unit 7 – I/O Interfacing 17

Prof. Swati R Sharma Unit 7 – I/O Interfacing 19

Prof. Swati R Sharma Unit 7 – I/O Interfacing 20

 Port A contains 8-bit I/O latch/buffer.

Prof. Swati R Sharma Unit 7 – I/O Interfacing 21

Prof. Swati R Sharma Unit 7 – I/O Interfacing 23

Prof. Swati R Sharma Unit 7 – I/O Interfacing 24

Prof. Swati R Sharma Unit 7 – I/O Interfacing 25

0  BSR Mode 1  I/O Mode

Simple I/O Handshake I/O Bidirectional

Port C: bits are Port B:either

Prof. Swati R Sharma Unit 7 – I/O Interfacing 26

 Simple I/O for port A,B and C

Prof. Swati R Sharma Unit 7 – I/O Interfacing 27

 Handshake signal are exchanged between MPU

Prof. Swati R Sharma Unit 7 – I/O Interfacing 28

 In this mode, Port A can be configured as the

Prof. Swati R Sharma Unit 7 – I/O Interfacing 29

 It consists of three 8-bit IO ports i.e. PA, PB, and PC.

Prof. Swati R Sharma Unit 7 – I/O Interfacing 30

8255A: Control Register

Prof. Swati R Sharma Unit 7 – I/O Interfacing 32

8255A: Control Word

Prof. Swati R Sharma Unit 7 – I/O Interfacing 34

and A1 are at logic1.

Prof. Swati R Sharma Unit 7 – I/O Interfacing 35

1= I/O Mode PORTACu(PCMode

Prof. Swati R Sharma Unit 7 – I/O Interfacing 36

 Configure Port A and Port CU as output

Prof. Swati R Sharma Unit 7 – I/O Interfacing 37

Prof. Swati R Sharma Unit 7 – I/O Interfacing 38

1. MVI A,D3H ;Load accumulator with controlword (1110 0011)

Prof. Swati R Sharma Unit 7 – I/O Interfacing 39

BSR Mode 1= Set

can be set or reset depending on D0 of

Prof. Swati R Sharma Unit 7 – I/O Interfacing 41

Prof. Swati R Sharma Unit 7 – I/O Interfacing 43

 Manage eight levels of interrupts.

Prof. Swati R Sharma Unit 7 – I/O Interfacing 44

8259 Internal Block Diagram