Target Hardware Debugging

Boundary scan
 TARGET HARDWARE DEBUGGING

● Even though firmware is bug free embedded

product need not function as per expected
behavior
● This is because of dry soldering, missing
connections, un-noticed errors in PCB etc.
● Debugging the target board is the only way to
sort out these issues
 Contd..

Hardware debugging involves

•  Monitoring various signals of target board

• Checking connection between components

•  Circuit continuity checking

 Hardware debugging tools
Hardware debugging tools are

⮚ Magnifying Glass(Lens)
⮚  Multimeter
⮚ Digital CRO
⮚ Logic Analyzer
⮚ Function Generator
 BOUNDARY SCAN
What is Boundary Scan?

Boundary Scan is a methodology allowing complete

controllability and observability of the boundary pins of
a JTAG compatible device via software control
BOUNDARY SCAN ARCHITECTURE
Cont..
● JTAG port contains five signal lines viz. TDI, TDO, TCK,
TRST and TMS, which together forms Test Access Port
(TAP). Each device will have its own TAP.
● The TDI pin of TAP of PCB is connected to the TDI pin
of the first device. TDO pin off the first device is
connected to TDI pin of second device. Same way all
devices are interconnected. TDO of the last JTAG
device is connected to TDO pin of TAP of PCB.
● TCK and TMS line of the devices are connected to
clock and test mode select line of TAP of PCB. This
forms a boundary scan path.
cont..
● The boundary scan cells can be operated in
following modes –
❏ Normal mode
❏ Capture mode
❏ Update mode .

❏ Shift mode

● ICs supporting boundary scan contain additional

registers.
❏ Instruction register
❏ Bypass register
 BOUNDARY SCAN PRINCIPLE
How does it work ?
the top level schematic of the test logic defined by IEEE
Std 1149.1 includes three key blocks:
Tap controller
This responds to the control sequences supplied
through the test access port (TAP) and generates the
clock and control sequence signal required for
correction operation of the other circuit blocks
Instruction Register
This shift register based circuit is serially loaded with
the instruction that selects an operation to be
performed
Cont..
Data registers
These are a bank of shift register based circuits. The
stimuli required by an operation are serially loaded into
the data register selected by the current instruction.
Following execution of the operation, results can be
shifted out for examination.
IEEE 1149.1 a standard 4 wire serial protocol ,that
established the details of access to any chip with
a JTAG port
• boundary scan testing of IC’s and boards
• Debug Embedded devices
• System level debug capability
 REAL JTAG APPLICATIONS
● Debugging.
● Storing firmware.
● Boundary scan testing.
● Reduced pin count JTAG(IEEE 1149.7)
● Primitives.
● Boundary scan register.
● Scan access to chips,boards,system for:
Design verification debug
Manufacturing test
● Access built- in -self -test(BIST)
 DATA REGISTERS
● The device ID registers (IDR) reads -out an
identification number which is hard wired into the
chip.
● BSR - “Boundary-scan register”,the main register
for passing data to the boundary-scan cells.
● BYPASS - A single-bit thru register, connecting TDi
to TDO without first passing through the boundary-
scan cells.
● EXTEST-perform an “external” boundary-scan test
using boundary scan cells.
 JTAG Test access port(contd)
There are four required signal in the JTAG
standard, and one optional signal.
● Test data input (TDI) pins
● Test data output (TDO) pins
● A test clock pin (TCK)
● A test mode select pin (TMS) for controlling
the TAP state machine
● The test reset pin (TRST) ,which forces the
state machine into the reset state.