INTERRUPT

EXPANDING HW INTERRUPT
PRESENTED BY: DR. SYED AQEEL HAIDER
EXPANDING INTERRUPT STRUCTURE

 8088/8086 microprocessor has a single INTR input for receiving interrupts from I/O devices.
 If no technique is employed to multiplex interrupt signals coming from different I/O devices, only one interrupt
signal may be connected with INTR input of 8088/8086 microprocessor.
 Following methods may be employed to expand hardware interrupt interface of 8088/8086 microprocessor:
 Using the 74ALS244 Buffer
 Daisy-chain Method
 8259 Programmable Interrupt Controller
USING 74ALS244 BUFFER TO EXPAND INTERRUPT STRUCTURE
USING 74ALS244 BUFFER TO EXPAND INTERRUPT STRUCTURE

 The modification shown in Figure 12–13 allows to accommodate up to seven additional interrupt inputs.
 The only hardware change is the addition of an eight-input NAND gate, which provides the INTR signal to the
microprocessor when any of the IR inputs becomes active.
 In case, only one IR input is active, interrupt vectors are listed in Table 12-1.
 If two or more interrupt request inputs are simultaneously active, a new interrupt vector is generated. For
example, if IR0 and IR1 are both active, the interrupt vector generated is FCH (252). Priority is resolved at this
location.
 If the input IR0 is to have the higher priority, the vector address for IR0 is stored at vector location FCh.
 The entire top half of the vector table and its 128 interrupt vectors must be used to accommodate all possible
conditions of these seven interrupt request inputs. This seems wasteful, but in many dedicated applications it is a
cost-effective approach to interrupt expansion.
DAISY-CHAIN METHOD FOR INTERRUPT EXPANSION
 PORT A – MODE 1 INPUT

Input
PORT A
Device
 If ‘INTE A’ is set then IBF will be available at INTR
INTE STB
 Bit 4 of Port C is to be set for INTE A = 1 A
PC4
(Strobe)
 Hence, interrupt processed I/O is activated PC5 IBF
(Input Buffer Full)
 Command Byte B:
For setting PC4 : 0 * * * 1 0 0 1 = 00001001 = 09h

PC3 INTR
(Interrupt Request)
 PORT B – MODE 1 INPUT

Input
PORT B
Device
 If ‘INTE B’ is set then IBF will be available at INTR
INTE STB
 Bit 2 of Port C is to be set for INTE B = 1 B
PC2
(Strobe)
 Hence, interrupt processed I/O is activated PC1 IBF
(Input Buffer Full)
 Command Byte B:
For setting PC4 : 0 * * * 0 1 0 1 = 00000101 = 05h

PC0 INTR
(Interrupt Request)
 PORT A – MODE 1 OUTPUT

Outpu
PORT A t
Device
 If ‘INTE A’ is set then OBF will be available at INTR
INTE ACK
 Bit 6 of Port C is to be set for INTE A = 1 A
PC6
(Acknowledgement)
 Hence, interrupt processed I/O is activated PC7 OBF
(Output Buffer Full)
 Command Byte B:
For setting PC4 : 0 * * * 1 1 0 1 = 00001101 = 0Dh

PC3 INTR
(Interrupt Request)
 PORT B – MODE 1 OUTPUT

Outpu
PORT B t
Device
 If ‘INTE B’ is set then OBF will be available at INTR
INTE ACK
 Bit 2 of Port C is to be set for INTE A = 1 B
PC2
(Acknowledgement)
 Hence, interrupt processed I/O is activated PC1 OBF
(Output Buffer Full)
 Command Byte B:
For setting PC4 : 0 * * * 0 1 0 1 = 00000101 = 05h

PC0 INTR
(Interrupt Request)
DAISY-CHAIN METHOD FOR INTERRUPT EXPANSION
 Expansion by means of a daisy-chained interrupt is in many ways better than using the 74ALS244 because it
requires only one interrupt vector.
 The task of determining priority is left to the interrupt service procedure.
 Setting priority for a daisy-chain does require additional software execution time, but in general this is a much
better approach to expanding the interrupt structure of the microprocessor.
 Figure 12–14 illustrates a set of two 82C55 peripheral interfaces with their four INTR outputs daisy-chained and
connected to the single INTR input of the microprocessor. If any interrupt output becomes a logic 1, so does the
INTR input to the microprocessor causing an interrupt.
 Example 12–7 illustrates the interrupt service procedure that responds to the daisy-chain interrupt request. The
procedure polls each 82C55 and each INTR output to decide which interrupt service procedure to utilize.
8259 PROGRAMMABLE INTERRUPT CONTROLLER

 Available in 28-pin DIP.

D7 – D0 ………………… 8
IR7 – IR0 ……………….. 8
A0, CS ……………………. 2
INT, INTA ……………….. 2
RD, WR ………………….. 2
SP / EN …………………… 1
CAS2 – CAS0 …………… 3
VCC, GND ………………. 2
 8259 PROGRAMMABLE INTERRUPT CONTROLLER

Master 8259A Address : 80h – 81h

1
Slave1 8259A Address : 88h – 89h Input
Slave2 8259A Address : 90h – 91h Device Output
D0 SP/EN IR0 Device
D7 – D0 of 8088 : IR1 0
Input
D7 IR2 Device
IR3 8259 D0 SP/EN IR0
INTR of 8088 INT IR4 (Slave1) : IR1
INTA of 8088 INTA 8259 IR5 D7 IR2
A0 of 8088 A0 (Master) IR6 INT IR3
IR7 INTA 8259 IR4
A1 A1
A2
A0 (Slave2) IR5
A2 IR6
Output
A3 A3 Device
A4 CS A4 CS IR7
A5 A5
A6 A6
A7 A7
CAS0 CAS0
CAS1 CAS1
CAS2 CAS2
8259 COMMAND WORDS

 The 8259A is programmed by initialization and operation command words.

 Initialization command words (ICWs) are programmed before the 8259A is able to function in the system and
dictate the basic operation of the 8259A.
 Operation command words (OCWs) are programmed during the normal course of operation. The OCWs control
the operation of the 8259A.
INITIALIZATION SEQUENCE
ICW1

ICW2 Is IC4 = 0
? Yes

No
Is Yes
SNGL=
ICW4
1?

No

ICW3 READY TO ACCEPT

INTERRUPT REQUESTS
 8259 PROGRAMMABLE INTERRUPT CONTROLLER

Master 8259A Address : 80h – 81h

1
Slave1 8259A Address : 88h – 89h Input
Slave2 8259A Address : 90h – 91h Device Output
D0 SP/EN IR0 Device
D7 – D0 of 8088 : IR1 0
Input
D7 IR2 Device
IR3 8259 D0 SP/EN IR0
INTR of 8088 INT IR4 (Slave1) : IR1
INTA of 8088 INTA 8259 IR5 D7 IR2
A0 of 8088 A0 (Master) IR6 INT IR3
IR7 A0 of 8088 INTA 8259 IR4
A1 A1
A2
A0 (Slave2) IR5
A2 IR6
Output
A3 A3 Device
A4 CS A4 CS IR7
A5 A5
A6 A6
A7 A7
CAS0 CAS0
CAS1 CAS1
CAS2 CAS2
ICW1

A0 D7 D6 D5 D4 D3 D2 D1 D0
0 A7 A6 A5 1 LTIM ADI SNGL IC4

A7 A6 A5 : * * * (for 8088 microprocessor)

LTIM : 0 – Edge-triggered Interrupt Inputs

1 – Level-triggered Interrupt Inputs

ADI : * (for 8088 microprocessor)

SNGL : 0 – Cascaded Mode

1 – Single Mode

IC4 : 0 – ICW4 not needed

1 – ICW4 needed
ICW2

A0 D7 D6 D5 D4 D3 D2 D1 D0
1 T7 T6 T5 T4 T3 * * *

T7 – T3 of Interrupt Vector Address (for 8088 microprocessor)

ICW3
Master device:
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 S7 S6 S5 S4 S3 S2 S1 S0

Sn : 0 – IRn input does not have a slave

1 – IRn input has a slave
Slave device:
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 ID2 ID1 ID0

Select IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

ID0 0 1 0 1 0 1 0 1
ID1 0 0 1 1 0 0 1 1
ID2 0 0 0 0 1 1 1 1
ICW4

A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 SFNM BUF M/S AEOI µPM

SFNM : 0 – Special Fully Nested Mode not selected

1 – Special Fully Nested Mode selected
BUF M/S Mode
AEOI : 0 – Normal End of Interrupt 0 * Non-buffered Mode
1 – Automatic End of Interrupt 1 0 Buffered Mode Slave

µPM : 0 – 8085 microprocessor Mode 1 1 Buffered Mode Master

1 – 8088 microprocessor Mode
EXAMPLE FOR INITIALIZATION OF 8259A PIC
A0 D7 D6 D5 D4 D3 D2 D1 D0
0 A7 A6 A5 1 LTIM ADI SNGL IC4

Q: Consider a 8088 microprocessor based system where two 8259A PIC are connected in cascade mode. Master is
interfaced for the addresses 80h – 81h while slave is interfaced at address 88h – 89h. Write command words for
following:
 Master device: Special Fully Nested Mode is selected, interrupt request inputs are edge triggered, automatic end
of interrupt is selected, buffered operation and interrupt vectors 60h – 67h are assigned to IR pins.
 Slave device: Special Fully Nested Mode is selected, interrupt request inputs are level triggered, normal end of
interrupt is selected, connected at IR5 of master and interrupt vectors 68h – 6Fh are assigned to IR pins.
Solution:
Master device: Slave device:
ICW1: * * * 1 0 * 0 1 = 0 0 0 1 0 0 0 1 = 11h ICW1: * * * 1 1 * 0 1 = 0 0 0 1 1 0 0 1 = 19h
MOV AL , 11h MOV AL , 19h
OUT 80h , AL ; A0 = 0 required OUT 88h , AL ; A0 = 0 required
EXAMPLE FOR INITIALIZATION OF 8259A PIC
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0
T7
S7 0
T6
S6 0
T5
S5 0
T4
SFNM
S4 0
T3
BUF
S3 ID2
*
M/S
S2 ID1
*
AEOI
S1 ID0
*
µPM
S0

Master device: ICW2: 0 1 1 0 1 * * * = 68h (IV # 68h – 6Fh)

ICW2: 0 1 1 0 0 * * * = 60h (IV # 60h – 67h)
MOV AL , 60h
OUT 81h , AL ; A0 = 1 required
ICW3: 0 0 1 0 0 0 0 0 = 20h
MOV AL , 20h
OUT 81h , AL ; A0 = 1 required
ICW4: 0 0 0 1 1 1 1 1 = 1Fh
MOV AL , 1Fh
OUT 81h , AL ; A0 = 1 required
Slave device:
MOV AL , 68h
OUT 89h , AL ; A0 = 1 required
ICW3: 0 0 0 0 0 1 0 1 = 05h
MOV AL , 05h
OUT 89h , AL ; A0 = 1 required
ICW4: 0 0 0 1 1 0 0 1 = 19h
MOV AL , 19h
OUT 89h , AL ; A0 = 1 required
THANK YOU