BOUNDARY SCAN/JTAG

Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for

testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated
circuit (IC) level.
 The Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that
was standardized as the IEEE Std. 1149.1
The boundary-scan test architecture provides a means to test interconnects between integrated
circuits on a board without using physical test probes
ARCHITECTURE
 Test Access Port
• Test Access Port (TAP) includes these signals: ƒ

• Test Clock Input (TCK)

• Clock for test logic „ Can run at different rate from system clock

• ƒ Test Mode Select (TMS)

• Switches system from functional to test mode

• ƒ Test Data Input (TDI)

• Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions

• ƒ Test Data Output (TDO)

• Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers)

• ƒ Test Reset (TRST)

• Optional asynchronous TAP controller reset
 JTAG Instructions
 EXTEST
 Test the interconnection between chips.
 INTEST
 Test the internal logic of selected chip.
 BYPASS
 Bypass onechip and forward the test data to next Chip.
 SAMPLE/PRELOAD
 The boundary-scan register is accessible through data scans while the device remains functional. This is also
useful for preloading data into the boundary-scan register without interrupting the device's functional
behavior, prior to executing the EXTEST instruction.
 RUNBIST
 To run comprehensive Built-in Self Test logic.
 CLAMP
 to clamp outputs to predefined logic levels  
 HIGHZ
 To set all outputs to the disabled (high impedance) state.
THANK YOU