Checks to be done before CTS:

1.Hierachical pins should not be defined as a clock source

2.Generated clock should have a valid master clock source
a)A generated clock does not have a valid master clock source
- The master clock specified in create_generated_clock does not exit
-The master clock specified in create_generated_clock does not drive source
pin of the generated clock
-The source pin of the generated clock is driven by multiple clock and some
of the master clocks are not specified with create_generated_clock
2.Clock(Master or generated) with no sinks
3.Looping clock
4.Casecaded clock with an un-synthesized clock tree in it’s fanout
5.Multiple clock per register propagation not enabled, but the design contains
overlapping clocks
6.Clock tree exceptions should not be ignored.
7.Stop pin or float pin defined on an output pin is an issue.
Sanity checks need to be done before CTS
• Check legality.
• Check power stripes, standard cell rails & also verify PG connections.
• Timing QoR (setup should be under control).
•  Timing DRVs.
•  High Fanout nets (like scan enable / any static signal).
•  Congestion (running CTS on congested design / design with
congestion hotspots can create more congestion & other issues
(noise / IR)).
•  Remove don’t_use attribute on clock buffers & inverters.
•  Check whether all pre-existing cells in clock path are balanced cells
(CK* cells).
•  Check & qualify don’t_touch, don’t size attributes on clock
components
Preparations
•  Understand clock structure of the design & balancing
requirements of the designs. This will be help in coming with
proper exceptions to build optimum clock tree.
•  Creating non-default rules (check whether shielding is required).
•  Setting clock transition, capacitance & fan-out.
•  Decide on which cells to be used for CTS (clock buffer / clock
inverter).
•  Handle clock dividers & other clock elements properly. Come up
with exceptions.
•  Understand latency (from Full chip point of view) & skew targets.
•  Take care of special balancing requirements.
•  Understand inter-clock balancing requirements.
Difference between High Fan-out Net Synthesis (HFNS) &
Clock Tree Synthesis:
• Clock buffers and clock inverter with equal rise and fall
times are used. Whereas HFNS uses buffers and
inverters with a relaxed rise and fall times.
• HFNS are used mostly for reset, scan enable and other
static signals having high fan-outs. There is not stringent
requirement of balancing & power reduction.
• Clock tree power is given special attention as it is a
constantly switching signal. HFNS are mostly performed
for static signals and hence not much attention to
power is needed.
• NDR rules are used for clock tree routing.
Why buffers/inverters are inserted?
• Balance the loads.
• Meet the DRC’s (Max Tran/Cap etc.).
• Minimize the skew.

What is the difference between clock buffer and normal buffer?

• Clock buffer have equal rise time and fall time, therefore pulse width violation is avoided.
• In clock buffers Beta ratio is adjusted such that rise & fall time are matched. This may increase
size of clock buffer compared to normal buffer.
• Normal buffers may not have equal rise and fall time.
• Clock buffers are usually designed such that an input signal with 50% duty cycle produces an
output with 50% duty cycle.

CTS Goals
• Meet the clock tree DRC.
– Max. Transition.
– Max. Capacitance.
– Max. Fanout.
• Meet the clock tree targets.
– Minimal skew.
– Minimum insertion delay.