Universal Asynchronous receiver and transmitter(UART)

BATCH 2: NARENDRA AND SHIVA

INTRODUCTION

 A Universal Asynchronous Receiver and Transmitter (UART) is an integrated circuit which plays an important role in serial
communication.
 UART is a hardware communication protocol that uses asynchronous serial communication with configurable speed
 UART is being used in several applications like GPS Receivers, Bluetooth Modules, GSM and GPRS Modems, Wireless
Communication Systems, RFID-based applications, etc.
 In this communication, there are two types of UARTs such as transmitting UART and receiving UART, and the communication
between these two can be done explicitly by each other.
FUNCTIONS OF UART

There are various functions of UART which are as follows −

• It can change parallel data into serial data for outbound communications
• It can change serial data into parallel data for inbound communications
• It can add a parity checking bit on outbound transmissions and tests the parity bit for inbound transmissions
• It can handle interrupt requests and device administration, which can need the computer and the device to organize
the speed of operation.
DATA FRAME

 A UART frame consists of 1 start bit, a number of data bits, an optional parity bit and 1, 1.5, or 2 stop bits. The
start bit goes low for one bit time, then a number of data bits are transmitted, least significant bit first, the number
of data bits ranges is typically 5, 6, 7, or 8.
BAUD RATE GENERATION

 Baud rate generator module divides the system clock by a divisor (N) to provide standard baud rate clock(bclk).
 Industry standard system clock frequencies for UART are 1,8432MHz, 2.4576MHz, 3.072MHz.
 The divisor N can be calculated using the formula

N= frequency of system clock(1.8432 Mhz) / maximum baud rate frequency(38400)* No.of samples per
bit(8)*2
=3( Duty cycle of clkdiv(divided by 3)33.33%)
BLOCK DIAGRAM
INPUT PORT DECLARATIONS

Transmitter:
 Tx_data (parallel data transmission)
 Tx_start (transmission start bits)
 Clk(for to enable transmitter)

Receiver:
 Rxd(serial receiver data)
 Clk (clk enable)

Baudrate:
 bclk
 Enable
OUTPUT PORT DECLARATIONS

Transmitter:
 Tx_data(transmitted data)
 Tx_done(enables if transmission completes)

Receiver:
 Rxd_data[7:0] (received serial data of 8-bit)
 Rx_ready (enables if received data)

Baudrate:
 bclkx8(baudrate output)