Bus

Single Bus

Processor Memory

Bus

I/O device 1 I/O device n

 Only one source/destination pair of units can use this bus to transfer
data at any one time.
 The bus consists of three sets of lines used to carry address, data, and
control signals.
 I/O device interfaces are connected to these lines, for an input device.
 Each I/O device is assigned a unique set of addresses for the registers in
its interface.
 When the processor places a particular address on the address lines, it is
examined by the address decoders of all devices on the bus.
 The device that recognizes this address responds to the commands issued
on the control lines.
 The processor uses the control lines to request either a Read or a Write
operation, and the requested data are transferred over the data lines.
 When I/O devices and the memory share the same address space, the
arrangement is called memory-mapped I/O.
 Any machine instruction that can access memory can be used to transfer
data to or from an I/O device.
 Bus Operation
 A bus requires a set of rules, often called a bus protocol, that govern how the
bus is used by various devices.

 The bus protocol determines when a device may place information on the bus,
when it may load the data on the bus into one of its registers, and so on.

 One control line, usually labelled R/W, specifies whether a Read or a Write
operation is to be performed.
 As the label suggests, it specifies Read when set to 1 and Write when set to 0.
 The bus control lines also carry timing information.
 In any data transfer operation, one device plays the role of a master.

 This is the device that initiates data transfers by issuing Read or Write
commands on the bus. Normally, the processor acts as the master, but other
devices may also become masters as we will see in the device addressed by the
master is referred to as a slave.
 Buses

Types of Buses:

1. Synchronous Bus.

2. Asynchronous Bus.
Synchronous Bus
 On a synchronous bus, all devices derive timing information from a control
line called the bus clock, shown at the Fig. The signal on this line has two
phases: a high level followed by a low level.
 The two phases constitute a clock cycle. The first half of the cycle between the
low-to-high and high-to-low transitions is often referred to as a clock pulse.
 Let us consider the sequence of signal events during an input (Read)
operation.
 At time t0, the master places the device address on the address lines and
sends a command on the control lines indicating a Read operation.
 The command may also specify the length of the operand to be read.
Information travels over the bus at a speed determined by its physical and
electrical characteristics.
 The clock pulse width, t1 − t0, must be longer than the maximum
propagation delay over the bus. Also, it must be long enough to allow all
devices to decode the address and control signals, so that the addressed device
(the slave)can respond at time t1 by placing the requested input data on the data
lines.
 At the end of the clock cycle, at time t2, the master loads the data on the data
lines into one of its registers.
Asynchronous Bus.
 handshake protocol between the master and the slave. A handshake is
an exchange of command and response signals between the master and
the slave. It is a generalization of the way the Slave-ready signal is used
in Figure .
 A control line called Master-ready is asserted by the master to indicate
that it is ready to start a data transfer.
 The Slave responds by asserting Slave-ready data transfer controlled by a
handshake protocol proceeds as follows.
 The master places the address and command information on the bus.
 Then it indicates to all devices that it has done so by activating the
Master-ready line.
 This causes all devices to decode the address. The selected slave
performs the required operation and informs the processor that it has
done so by activating the Slave-ready line.
 The master waits for Slave-ready to become asserted before it removes
its signals from the bus. In the case of a Read operation, it also loads
the data into one of its registers.
 Bus arbitration
 Processor and DMA controllers both need to initiate data transfers
on the bus and access main memory.
 The device that is allowed to initiate transfers on the bus at any given
time is called the bus master.
 When the current bus master relinquishes its status as the bus
master, another device can acquire this status.
 The process by which the next device to become the bus master is
selected and bus mastership is transferred to it is called bus
arbitration.
 Centralized arbitration:
 A single bus arbiter performs the arbitration.
 Distributed arbitration:
 All devices participate in the selection of the next bus master.
Centralized arbitration
• Bus arbiter may be the processor or a separate unit connected to the
bus.

• Normally, the processor is the bus master, unless it grants bus

membership to one of the DMA controllers.

• DMA controller requests the control of the bus by asserting the Bus
Request (BR) line.

• In response, the processor activates the Bus-Grant1 (BG1) line, indicating

that the controller may use the bus when it is free.

• BG1 signal is connected to all DMA controllers in a daisy chain fashion.

• BBSY signal is 0, it indicates that the bus is busy. When BBSY becomes
1, the DMA controller which asserted BR can acquire control of the bus.
Distributed arbitration
 All devices waiting to use the bus share the responsibility of
carrying out the arbitration process.
 Arbitration process does not depend on a central arbiter and hence
distributed arbitration has higher reliability.
 Each device is assigned a 4-bit ID number.
 All the devices are connected using 5 lines, 4 arbitration lines to
transmit the ID, and one line for the Start-Arbitration signal.
 To request the bus a device:
 Asserts the Start-Arbitration signal.
 Places its 4-bit ID number on the arbitration lines.
 The pattern that appears on the arbitration lines is the logical-OR of
all the 4-bit device IDs placed on the arbitration lines.
 Advantages of asynchronous bus:
 Eliminates the need for synchronization between the sender and the
receiver.
 Can accommodate varying delays automatically, using the Slave-
ready signal.
 Disadvantages of asynchronous bus:
 Data transfer rate with full handshake is limited by two-round trip
delays.
 Data transfers using a synchronous bus involves only one round
trip delay, and hence a synchronous bus can achieve faster rates.
 Interface circuits
 I/O interface consists of the circuitry required to connect an I/O device to
a computer bus.
 Side of the interface which connects to the computer has bus signals for:
 Address,
 Data
 Control
 Side of the interface which connects to the I/O device has:
 Datapath and associated controls to transfer data between the interface
and the I/O device.
 This side is called as a “port”.
 Ports can be classified into two:
 Parallel port
 Serial port
18
Interface circuits
 Parallel port transfers data in the form of a number of bits, normally 8 or 16 to or from the device.

 Serial port transfers and receives data one bit at a time.

 Processor communicates with the bus in the same way, whether it is a parallel port or a serial port.

 Conversion from the parallel to serial and vice versa takes place inside the interface circuit.

 Parallel port uses a multiple pin connector between the device and the processor, and a cable with as
many wires as the number of bits transferred simultaneously.

 Suitable for devices that are physically close to the computer.

 Serial port uses a single pin connector to between the device and the processor:

 Useful for devices that are at a longer distance.

19
Parallel port
Data

Address
D A T AIN
Data
Encoder

R / W and K e yboard
Processor SIN
debouncing switches

Master -ready circuit

V alid
Input
Sla v e-ready
interf ace

•Keyboard is connected to a processor using a parallel port.

•Processor is 32-bits and uses memory-mapped I/O and the asynchronous bus protocol.

•On the processor side of the interface we have:

20
- Data lines. - Address lines - Control or R/W line - Master-ready signal - Slave-ready signal
 Parallel port (contd..)

Data

Address
D AT AIN Data
Encoder
R / W and K e yboard
Processor SIN
debouncing switches
Master -ready circuit
V alid
Input
Sla v e-ready
interf ace

•On the keyboard side of the interface:

- Encoder circuit which generates a code for the key pressed.
- Debouncing circuit which eliminates the effect of a key bounce (a single key stroke may appear as multiple events
to a processor).
- Data lines contain the code for the key.
- Valid line21changes from 0 to 1 when the key is pressed. This causes the code to be loaded into DATAIN and SIN
to be set to 1.
Parallel port
Data

Address Data
D A T A OUT

R / W SOUT
Processor
CPU V alid Printer

Master -ready
Output Idle
Sla v e-ready interf ace

•Printer is connected to a processor using a parallel port.

•Processor is 32 bits, uses memory-mapped I/O and asynchronous bus protocol.
•On the processor side:
- Data lines. - Address lines - Control or R/W line. - Master-ready signal and
22
- Slave-ready signal.
 Parallel port (contd..)
Data

Address Data
D A TA OUT

R / W SOUT
Processor
CPU V alid Printer

Master -ready
Output Idle
Sla v e-ready interf ace

•On the printer side:

- Idle signal line which the printer asserts when it is ready to accept a character.
This causes the SOUT flag to be set to 1.
- Processor places a new character into a DATAOUT register.
- Valid signal, asserted by the interface circuit when it places a new character on the
23

data lines.
 Serial port
 Serial port is used to connect the processor to I/O devices that
require transmission of data one bit at a time.

 Serial port communicates in a bit-serial fashion on the device side

and bit parallel fashion on the bus side.

 Transformation between the parallel and serial formats is

achieved with shift registers that have parallel access
capability.

 Speed of transmission of the data over a serial interface is

known as the “bit rate”.
24
 Standard I/O interfaces
 I/O device is connected to a computer using an interface circuit.

 Do we have to design a different interface for every combination of an I/O

device and a computer?

 A practical approach is to develop standard interfaces and protocols.

 A personal computer has:

 A motherboard which houses the processor chip, main memory and

some I/O interfaces.

 A few connectors into which additional interfaces can be plugged.

 Processor bus is defined by the signals on the processor chip.

 Devices which require high-speed connection to the processor are

27

connected directly to this bus.

 Standard I/O interfaces
 Because of electrical reasons only a few devices can be connected directly to
the processor bus.

 Motherboard usually provides another bus that can support more devices.

 Processor bus and the other bus (called as expansion bus) are
interconnected by a circuit called “bridge”.

 Devices connected to the expansion bus experience a small delay in data

transfers.

 Design of a processor bus is closely tied to the architecture of the processor.

 No uniform standard can be defined.

 Expansion bus however can have uniform standard defined.

28
 Standard I/O interfaces (contd..)
Main
Processor
memory
Bridge circuit translates
signals and protocols from
Processor b us processor bus to PCI bus.

Bridge

PCI b us
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller interf ace controller interf ace

SCSI b us
IDE
disk
V ideo

Disk CD-R OM
controller controller

CD-
Disk 1 Disk 2 R OM K e yboard Game

29
 A number of standards have been developed for the
expansion bus.

 Some have evolved by default.

 For example, IBM’s Industry Standard Architecture.

 Three widely used bus standards:

 PCI (Peripheral Component Interconnect)

 SCSI (Small Computer System Interface)

 USB (Universal Serial Bus)

30
 Standard I/O Interface

 1. PCI [Peripheral Component Inter Connect]

 2. SCSI [Small Computer System Interface]

 3. USB [Universal Serial Bus]

 1. PCI [Peripheral Component Interconnect]

 A Peripheral Component Interconnect Bus (PCI bus) connects the CPU and

expansion boards such as modem cards, network cards and sound cards.

 These expansion boards are normally plugged into expansion slots on the
motherboard.

 Peripheral Component Interconnect, or PCI, is a connection system to allow add-

in cards for your computer to interact with your microprocessor.

 The PCI cards get installed into PCI expansion slots which are generally on your
motherboard.
 SCSI [Small Computer System Interface]

 A System Interface controller provided a bridge between a hard

disk drive's low-level interface and a host computer, which
needed to read blocks of data.

 A Small Computer Systems Interface (SCSI) is a standard

interface for connecting peripheral devices to a PC.

 Depending on the standard, generally it can connect up to 16

peripheral devices using a single bus including one host adapter.

 SCSI is used to increase performance, deliver faster data

transfer transmission and provide larger expansion for devices
such as CD-ROM drives, scanners, DVD drives and CD writers.
 USB [Universal Serial Bus]
 The Universal Serial Bus (USB) is technology that allows a person to
connect an electronic device to a computer. It is a fast serial bus.

 It is mostly used on personal computers. ... Most people use USB for

computer mice, keyboards, scanners, printers, digital cameras,
and USB flash drives.
benefits
USB-2 USB-3
 Input/Output Processor
 An input-output processor (IOP) is a processor with direct memory access
capability.

 In this, the computer system is divided into a memory unit and number of
processors.

 Each IOP controls and manage the input-output tasks.

 The IOP is similar to CPU except that it handles only the details of I/O
processing.

 The IOP can fetch and execute its own instructions. These IOP instructions are
designed to manage I/O transfers only.
Block Diagram Of I/O Processor
 Block Diagram Of I/O Processor
 The memory unit occupies the central position and can communicate with each
processor.

 The CPU processes the data required for solving the computational tasks. The IOP
provides a path for transfer of data between peripherals and memory. The CPU
assigns the task of initiating the I/O program.

 The IOP operates independent from CPU and transfer data between peripherals
and memory.
 The communication between the IOP and the devices is similar to the program control method
of transfer. And the communication with the memory is similar to the direct memory access
method.

 In large scale computers, each processor is independent of other processors and any processor
can initiate the operation.

 The CPU can act as master and the IOP act as slave processor. The CPU assigns the task of
initiating operations but it is the IOP, who executes the instructions, and not the CPU. CPU
instructions provide operations to start an I/O transfer. The IOP asks for CPU through
interrupt.

 Instructions that are read from memory by an IOP are also called commands to distinguish them
from instructions that are read by CPU. Commands are prepared by programmers and are
stored in memory. Command words make the program for IOP. CPU informs the IOP where
to find the commands in memory.
Thank You…