ARM Microcontroller

RISC and CISC Architecture

• Reduced Instruction Set Architecture (RISC) – 
The main idea behind this is to make hardware simpler by using an instruction set composed of a few basic steps for
loading, evaluating, and storing operations just like a load command will load data, a store command will store the data. 

• Complex Instruction Set Architecture (CISC) – 

The main idea is that a single instruction will do all loading, evaluating, and storing operations just like a multiplication
command will do stuff like loading data, evaluating, and storing it, hence it’s complex. 

• Both approaches try to increase the CPU performance 

• RISC: Reduce the cycles per instruction at the cost of the number of instructions per program. 

• CISC: The CISC approach attempts to minimize the number of instructions per program but at the cost of an increase in
the number of cycles per instruction. 
 RISC and CISC Architecture
Characteristic of RISC – 
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Fewer Data types.
• A pipeline can be achieved. 
Characteristic of CISC – 
• Complex instruction, hence complex instruction decoding.
• Instructions are larger than one-word size.
• Instruction may take more than a single clock cycle to get executed.
• Less number of general-purpose registers as operations get performed in memory itself.
• Complex Addressing Modes.
• More Data types. 
 RISC and CISC Architecture
• Example – Suppose we have to add two 8-bit numbers: 
• CISC approach: There will be a single command or instruction for this like ADD
which will perform the task.
• RISC approach: Here programmer will write the first load command to load
data in registers then it will use a suitable operator and then it will store the
result in the desired location.
• So, add operation is divided into parts i.e. load, operate, store due to which
RISC programs are longer and require more memory to get stored but require
fewer transistors due to less complex command. 
RISC and CISC Architecture
 ARM Microcontroller
• The ARM microcontroller stands for Advance RISC Machine; it is one of the
extensive and most licensed processor cores in the world.
• The first ARM processor was developed in the year 1978 by Cambridge
University, and the first ARM RISC processor was produced by the Acorn Group
of Computers in the year 1985.
• These processors are specifically used in portable devices like digital cameras,
mobile phones, home networking modules and wireless communication
technologies and other embedded systems due to the benefits, such as low
power consumption, reasonable performance, etc.
ARM Family
 ARM Architecture
• The ARM architecture processor is an
advanced reduced instruction set computing
[RISC] machine and it’s a 32bit reduced
instruction set computer (RISC)
microcontroller.
• It was introduced by the Acron computer
organization in 1987.
• This ARM is a family of microcontroller
developed by makers like ST
Microelectronics,Motorola, and so on.
• The ARM architecture comes with totally
different versions like ARMv1, ARMv2, etc.,
and, each one has its own advantage and
disadvantages.
 ARM Architecture
A[31:0]

Address Register Address

Incrementer

PC bus
The ARM cortex is a complicated microcontroller within the ARM PC

family that has ARMv7 design. REGISTER

BANK
There are 3 subfamilies within the ARM cortex family :

ALU bus

Control Lines
• ARM Cortex Ax-series INSTRUCCTION
DECODER
Multiplier

B bus
A bus
• ARM-Cortex Rx-series
• ARM-Cortex Mx-series SHIFT

The ARM Architecture

• Arithmetic Logic Unit A.L.U.
Instruction Reg.

• multiplier
Thumb to

• Barrel shifter Write Data Reg. Read Data Reg.

ARM
translator

• Control unit
• Register file D[31:0]
 ARM7TDMI A[31:0]

Block Diagram
Address Register Address
Incrementer

PC bus
PC

REGISTER
BANK

ALU bus

Control Lines
INSTRUCCTION
DECODER
Multiplier

B bus
A bus
SHIFT

A.L.U.
Instruction Reg.

Thumb to
ARM
Write Data Reg. Read Data Reg.
translator

D[31:0]
 ARM Architecture
• The ARM processor conjointly has other components like the Program status register, which contains the processor flags (Z, S,
V and C).
• The modes bits conjointly exist within the program standing register, in addition to  the interrupt and quick interrupt disable
bits;
• Some special  registers:  Some  registers are  used  like  the  instruction, memory data read and write registers and memory
address register.
• Priority encoder: The encoder  is  used  in  the  multiple  load  and  store instruction to point which register within the register
file to be loaded or kept .
• Multiplexers: several multiplexers are accustomed to the management operation  of  the processor buses.
• Because of the restricted project time, we tend to implement these components in a very behavioral model. Each component
is described with an entity.
• Every entity has its own architecture, which can be optimized for certain necessities depending on its application.
• This creates the design easier to construct and maintain.
 ARM Architecture
Arithmetic Logic Unit (ALU)
• The ALU has two 32-bits inputs. 
• The primary comes from the register file, whereas the other comes from the shifter. Status registers flags modified by the ALU
outputs. 
• The V-bit output goes to the V flag as well as the Count goes to the C flag. 
• Whereas the foremost significant bit really  represents  the  flag,  the  ALU  output  operation is  done by NORed to  get  the  Z  flag. 
• The ALU has a 4-bit function bus that permits up to 16 opcode to be implemented.
Multiplier Factor
• The multiplier factor has  32-bit inputs and the inputs return from the register file. 
• The multiplier output is barely  32-Least Significant  Bits of the merchandise. 
• The entity representation of the multiplier factor is shown in the above block diagram. 
• The multiplication starts  whenever  the  beginning 04 input goes active. 
• Pin of  the output goes high when finishing.
Booth’s algorithm
Booth Algorithm
Booth algorithm is a noteworthy multiplication algorithmic rule for 2’s
complement numbers. This treats positive and negative numbers uniformly.
Moreover, the runs of 0’s or 1’s within the multiplier factor are skipped over
without any addition or subtraction being performed, thereby creating
possible quicker multiplication. 

M: 7  (0111)
Q: 3  (0011)

-M: (-7)  (1001)

 n=4
A Q Q-1 Operation
0000 0011 0 A=A-M
0000
+1001
----------
Cycle-1 1001
1001 0011 0
1100 1001 1 ASR
1110 0100 1 ASR
Cycle-2
A=A+M
1110
+0111
---------
Cycle-3 0101 0101 (discard carry)
0010 1010 0 ASR
0001 0101 0 ASR

Cycle-4
 ARM Architecture
Barrel Shifter
• The barrel shifter features a 32-bit input to be shifted. 
• This input is coming back from the register file or it might be immediate data. 
• The shifter has different control inputs coming back from the instruction register.
• The Shift field within the instruction controls the operation of the barrel shifter. 
• This  field indicates the kind  of  shift  to  be  performed  (logical  left  or  right, arithmetic right or rotate right).
• The quantity by which the register ought to be shifted is contained in an immediate field within the instruction
or it might be the lower 6 bits of a register within the register file.
• The shift_val input bus is 6-bits, permitting up to 32 bit shift. The shifttype indicates the needed shift sort of  00,
01, 10, 11 are corresponding to shift left, shift right, an arithmetic shift right and rotate right, respectively. The
barrel shifter is especially created with multiplexers.
Using the Barrel Shifter: The Second Operand
Operand 1 Operand 2 Register, optionally with shift
operation
 Shift value can be either be:
 5 bit unsigned integer
 Specified in bottom byte of another
Barrel register.
Shifter  Used for multiplication by a power of
2
Example: ADD R1, R2, R3, LSL #2
(R2 + R3*4) -> R1

Immediate value
ALU  8 bit number, with a range of 0-255.
 Rotated right through even number of
positions
 Allows increased range of 32-bit
Result constants to be loaded directly into
registers
 ARM Architecture
Control Unit
• For any microprocessor, control unit is the heart of the whole process and it is
responsible for the system operation,so the control unit design is the most
important part within the whole design.
• The control unit is sometimes a pure combinational circuit design.
• Here, the control unit is implemented by easy state machine.
• The processor timing is additionally included within the control unit.
• Signals from the control unit are connected to each component within the
processor to supervise its operation.
 Current Processor Status Register

Flag bit Sets when

N-Negative In case of signed no. operations If result MSB=1 ;Indicates the result of operation is NEGATIVE
Z- Zero The result of operation is zero.
C- Carry The result causes an unsigned carry(carry out of MSB)
V-Overflow The result causes a signed overflow
Q- Saturation The result causes an overflow or saturation
I- Interrupt request Disable I = 1: Disables the IRQ
F- Fast interrupt request Disable F = 1: Disables the FIQ
T-Thumb instruction set If set T = 0: Processor in ARM state T = 1: Processor in Thumb state
 ARM Microcontroller Register Modes
• An ARM micrcontroller is a load store reducing instruction set computer architecture means the core cannot
directly operate with the memory.
• The data operations must be done by the registers and the information is stored in the memory by an address.
• The  ARM cortex-M3 consists of 37 register sets wherein 31 are general purpose registers and 6 are status
registers.
• The ARM uses seven processing modes to run the user task.
1. USER Mode
2. FIQ Mode
3. IRQ Mode
4. SVC Mode
5. UNDEFINED Mode
6. ABORT Mode
7. Monitor Mode
 ARM Pipelining
• A Pipelining is the mechanism used by RISC(Reduced instruction set computer) processors to execute
instructions, by speeding up the execution by fetching the instruction, while other instructions are being decoded
and executed simultaneously, which in turn allows the memory system and processor to work continuously.
• The pipeline design for each  ARM family is different.
• Pipelining is a design technique or a process which plays an important role in increasing the efficiency of data
processing in the processor of a computer and microcontroller. By keeping the processor in a continuous process
of fetching, decoding and executing called (FDE or F&E cycle).   
• ARM devices need pipelining because of it’s RISC. Each stage is equivalent to 1 cycle, that is n stages = n cycles.
 ARM Pipelining
• Fetch loads an instruction from memory.
• Decode identifies the instruction to be executed.
• Execute processes the instruction and writes the result back to the register.
• By over lapping the above stages of execution of different instructions, the speed of execution is increased.
• The pipelining allows the core to execute an instruction every cycle, which results in increased throughput.
ARM pipeline characteristics :
• The ARM pipeline doesn’t process an instruction until it passes completely through the execution stage.
• In the execution stage, the PC always points to the instruction address + 8 bytes.
• When the processor is in thumb state, PC always points to the instruction address + 4 bytes.
• While executing branch instructions or branching by direct modification of PC causes the ARM core
to flush it’s pipeline.
• As instruction in the execution stage will complete its execution even though an interrupt has been raised.
 ARM Pipelining
ARM 7 –
• It has 3 stage pipelining as shown in the figure.
• It can complete it’s process in 3 cycles.
• It has the basic F&E cycle leading to optimum throughput.
• This is why the ARM 7 has the lowest throughput as compared to that of it’s other family members.
• It processes 32bit data.
ARM 9 –
• Pipelining in ARM 9 is similar to ARM 7 but with 5 stages.
• It takes 5 cycles to complete the process.
• Fetch- It will fetch instructions from memory.
• Decode- It decodes the  instructions that were fetched in the first cycle.
• ALU –  It executes the instruction that has been decoded in the previous stage.
• LS1(Memory)  Loads/Stores the data specified by load or store instructions.
• LS2(Write) Extracts (zero or sign) extends the data loaded by  byte or half word load instruction.
• Because of an increase in stages and efficiency, the throughput is 10%-13% higher than ARM 7.
• Core frequency of ARM 9 is slightly higher than that of ARM 7.
• Similarly ARM 10 has 6 stage pilelining
 ARM-Cortex Microcontroller 
• In the  present days, the microcontroller vendors are offering 32-bit microcontrollers based on ARM cortex-m3 architecture.
• Many embedded system developers are starting to use these 32-bit microcontrollers for their  projects.
• The ARM microcontrollers supports for both low-level and high level programming languages. 
• Some of the traditional microcontroller architectures are made with many limitations therefore, difficult to use the high level programming language.
It is a reduced instruction set computing Controller
• 32-bit high performance central processing unit
• 3-stage pipeline and compact one
It has THUMB-2 technology
• Merges optimally with 16/32 bit instructions
• High performance
It supports tools and RTOS and its core Sight debug and trace
• JTAG or 2-pin serial wire debugs connection
• Support for multiple processors
Low power Modes
• It supports sleep modes
• Control the software package
Multiple power domains
• Nested vectored interrupt controller (NVIC)
• Low latency, low noise interrupts response
• No need for assembly programming