Operating Systems

Certificate Program in Software Development

CSE-TC and CSIM, AIT
September -- November, 2003

2. Computer-System Structures
(Ch. 2, S&G)

 Objective
– to give a (selective) overview of
computer system architectures

OSes: 2. Structs 1
 Contents

1. A Modern Computer System

2. Interrupts
3. I/O
4. Caching
5. Protection

OSes: 2. Structs 2
 1. A Modern Computer System
Fig 2.1, p.24

Line Printer

disk printer tape-drive

CPU
controller controller controller

system bus
memory I/O controller
controller I/O controller

memory
OSes: 2. Structs continued 3
  CPU and device controllers (drivers) can
execute concurrently.

 Access to shared memory must be

controlled.

 A hard-wired bootstrap program loads and

starts the OS kernel.

OSes: 2. Structs 4
 2. Interrupts

 Modern OSes are driven by interrupts

(traps) sent when events occur in hardware
or software.

 Types of events:
– completion of I/O, division by 0, system calls,
etc.

OSes: 2. Structs continued 5

  An interrupt causes the OS to stop its
current task, and switch execution to an
interrupt-processing routine.

 At the end of the routine, the old task is

resumed
– the old task’s details must be stored during the
interrupt processing

OSes: 2. Structs continued 6

  The addresses of the interrupt routines are
stored in a fixed segment of memory
(an interrupt vector).

 The OS selects a routine from the interrupt

vector based on the ‘type’ of the interrupt it
received.

OSes: 2. Structs continued 7

  Features of interrupts:
– disabling of other interrupts during interrupt
processing
– prioritisation

OSes: 2. Structs 8
 System Calls Fig 2.9, p.44

 System calls are implemented using interrupts.

resident
monitor
case n
:
1 read 2 perform I/O

trap to :
monitor :
system call n 3 return
:

user program
OSes: 2. Structs 9
 3. I/O

 Synchronous I/O
– the user process waits during I/O processing

 Asynchronous I/O
– control returns to the user without waiting for
the I/O to complete

OSes: 2. Structs 10
 I/O Forms Fig. 2.3, p.27

Synchronous Asynchronous
user requesting process user requesting process

device driver device driver

kernel interrupt handler kernel interrupt handler

hardware data hardware data
transfer transfer
time time

OSes: 2. Structs 11
 3.1. Synchronous I/O

 Waiting is done either with:

– a special wait instruction
– a busy-wait loop, such as:
loop: jmp loop

 A busy-wait generates instruction fetches,

and so may lead to contention with the I/O.
 Only one I/O process involved.
OSes: 2. Structs 12
 3.2. Asynchronous I/O

 Big advantage: the CPU is not affected

while slow I/O is carried out.

 Many I/O requests can be in action at once

– the implementation requires an I/O device
status table

OSes: 2. Structs 13
 I/O Device Status Table Fig 2.4, p.28

dev: card reader 1

status: idle
PID: 3445
dev: line printer 3
addr: 34556
status: busy
length: 1345
dev: disk unit 1
status: idle
dev: disk unit 2
status: idle file: xxx file: yyy
dev: disk unit 3 op: read op: write
status: busy addr: 23456 addr: 6543
: length: 2000 length: 500
:
OSes: 2. Structs 14
 3.3. Direct Memory Access (DMA)

 Device controllers transfer data blocks

to/from memory directly, bypassing the
CPU
– only one interrupt generated per block

– much faster than interrupt driven character

transfer

OSes: 2. Structs 15
 3.4. Memory Mapped I/O

 I/O device registers is mapped to memory

so that reads/writes to those memory
addresses go straight to the device
– used for fast and frequently used device

– e.g. video controller, serial port

OSes: 2. Structs 16
 4. Caching
 The cache is fast memory between the CPU
and main memory
– the CPU looks in the cache first for data
– new data taken from main memory is also
placed in the cache for quick access next time

 Instruction caching
 Cache management
– can affect performance drastically
OSes: 2. Structs 17
 Cache Coherency

 Must ensure that the data in the cache is

always the same as its original version in
main memory.

 Complicated by multiprocessor and

distributed environments
– several caches, replicated memory

OSes: 2. Structs 18
 5. Protection

 5.1. Dual-mode Operation

 5.2. Memory Protection
 5.3. CPU Protection

OSes: 2. Structs 19
 5.1. Dual-mode Operation

 User mode
 Monitor mode
– supervisor mode, root, superuser, system mode,
priveleged mode

 Implemented in hardware
 OS always runs in monitor mode

OSes: 2. Structs 20
 5.2. Memory Protection

 The interrupt vector must be protected from

modification by users.

 The interrupt processing routines must be

similarily protected.

OSes: 2. Structs 21
 Partitioning Memory Fig 2.7, p.40

0
monitor
256000
job 1
300040 300040
job 2 base register
420940
120900
job3
limit register
880000
job4
1024000
OSes: 2. Structs 22
 Fig 2.8, p.41

 Only addresses within the job’s memory

space are accessible.

base base + limit

address yes yes memory

CPU >= <
no no

trap to OS monitor -- addressing error

OSes: 2. Structs 23
 5.3. CPU Protection

 Each process is interrupted after a fixed

time
– this breaks infinite loops in poor code which
would otherwise hog the CPU

– allows the OS to time-slice users by context

switching

OSes: 2. Structs 24