Introduction

• Digital circuits may be either implementing combinational logic or

sequential logic
• This unit discusses all the basic building blocks of combinational
logic circuits
• These include Decoders, Encoder, Multiplexers, Demultiplexers,
Adders, Comparators etc
 Decoders

• A decoder is a circuit that changes a code into set of

signals or it is a multiple input and multiple output logic
circuit that converts coded inputs into coded outputs
• Input code has fewer bits than output code
• The mapping between input and output is one-to-one
i.e. no two input combinations will produce the same
output
• The most common binary decoders has n-inputs and 2n
outputs
Decoder circuit structure
▪ A binary decoder is used to
activate only one output
based upon the n-bit input
▪ Input is n-bit binary code
which represents any of
possible 2n values
▪ Output is 1 out of m code,
which contains m bits, out
of which only one is asserted
at any time
A General 2 –to- 4 Decoder
 A General 2 –to- 4 Decoder

Y0 = (EN . I1’ . I0’)

Y1 = (EN . I1’ . I0)
Y2 = (EN . I1 . I0’)
Y3 = (EN . I1 . I0)
 74x139 Dual 2 –to- 4 Decoder
• The 74x139 had dual 2 –to- 4 decoders
in a single chip and both are
independent
• The enable pins as well as the output
pins are active low
74x139 Dual 2 –to- 4 Decoder
 74x138 3 –to- 8 Decoder
• The 74x138 is a 3-t0-8 decoder
• It has three enable pins ( two are active
low) which have to be asserted for the
selected output to be asserted
• All the outputs are active low
• The three input pins C, B, A selects
which output to be asserted
Cascading two 3 to 8 decoders to realize 4 – 16 decoder
5 to 32 decoder
 Seven Segment Decoder

• A digit is displayed by illuminating a

subset of the seven line segments
• A seven segment decoder has 4-bit
BCD as its input code and a seven
segment code as the output
 Comparison of astable, monostable and bistable
multivibrator
Sr. Astable multivibrator Monostable Multivibrator Bistable multivibrator
No.
1. There are no stable states of output There is only one stable state of There are two stable staes of the
the output output.
2. Trigger input is not necessary for Trigger pulse is required for Trigger input is required for
changing the state of the output. changing the state of output. changing the state of output.

3. Used as rectangular, squarewave or Used as timer. Used as flip-flop.

ramp generator.

4. Number of quasi-stable state is 2. Number of quasi-stable state is 1. No quasi stable state.

5. Time for the two quasi stable states Time for the quasi stable state No quasi stabel states.
depends on RC time constant. The depends on RC time constant.
two quasi stable states can have
different intervals.

A. A. Lande, E & TC Dept

 Introduction

• A encoder assigns a binary code to an active input line

• In general the device input has more lines than output
• A binary encoder has 2n input lines and ‘n’ output lines i.e. input is 1 out

of 2n and output is a n-bit binary code

• For example if the encoder is a 4 to 2 encoder, then it has 4 input lines and
2 output lines
• The output is the 2-bit binary representation of the active input line
19
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There are 2n input lines and n Selection lines and only one output line
 Expanding Mux (or) DIGITAL IC’S OF MUX
Several digital Ic’s are available such as
• 74LS 151----(8 To 1 Mux)
• 74LS 150----(16 to 1 MUX)
• 74LS 157---(Quad two input Mux or 2 input 4-bit MUX)
• 74LS 153 –(Dual 4 to 1 MUX)
• It is possible to expand the range of inputs for Mux beyond the
available range in the IC.This can be accomplished by
interconnecting several mux
• Ex : two 74LS 151,8-to-1 Mux
It provides two outputs one is active high, other is active low.3 Select
inputs A,B,C
 74x151 8 input 1-bit Multiplexer

• It has 8(n) input lines each with 1 bit

of data
• It requires 3 select pins to select any
of the eight inputs
• No of select pins s= log2n
• It has an Enable pin which is active
low
• The inverted output is also available
Logic Diagram

Logic Diagram
Cascading 8 :1 Mux to realize 32 :1 Mux
The IC 74XX157 is a quad 2-input Mux which selects four bits of data from two sources under
the control of a common select input(S).the enable input (G’) is active low. Where E’ is high,
all of the outputs(Y) are forced low regardless of all other input conditions.