Mos/Bicmos Processes

U.Sravanajyothi
321206540004
1/2mtech
Introduction:
• BiCMOS technology was introduced in 1990s.
• BiCMOS is an evolved semiconductor technology that integrates two formerly separate
semiconductor technologies those of the BJT and CMOS.
• BiCMOS technology combines Bipolar and CMOS transistors in a single integrated circuit. By
retaining the benefits of Bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with
speed-power-density performance previously unattainable with either technology
individually.
• Used for high speed, low power and high functional VLSI circuits.
• The process step required for both cmos an bipolar are almost.
• Bicmos technology enables high performance integrated circuits but increases process
complexity.
Characteristics of bicmos:

• Improved speed over purely-cmos technology

• Low power dissipation than bipolar technology
• Flexible I/O for high performance
• Improved current drive over cmos
• Improved packing density over bipolar
• High input impedance
• Low output impedance
• High gain & low noise
BiCMOS Fabrication
 Steps for BiCMOS Fabrication
• The BiCMOS fabrication combines the process of fabrication of BJT and CMOS, but merely
variation is a realization of the base. The following steps show the BiCMOS fabrication process.

• Step1:  P-Substrate is taken as shown in the below figure

P substrate
• Step2:  The p-substrate is covered with the oxide layer

• Step3: A small opening is made on the oxide layer

• Step4: N-type impurities are heavily doped through the opening

• Step5: The P – Epitaxy layer is grown on the entire surface

• Step6: Again, entire layer is covered with the oxide layer and two openings are made through this
oxide layer.

Step7: From the openings made through oxide layer n-type impurities are diffused to form n-wells
• Step8: Three openings are made through the oxide layer to form three active devices.

Step9: The gate terminals of NMOS and PMOS are formed by covering and patterning the entire
surface with Thinox and Polysilicon.
• Step10: The P-impurities are added to form the base terminal of BJT and similar, N-type impurities
are heavily doped to form emitter terminal of BJT, source and drain of NMOS and for contact
purpose N-type impurities are doped into the N-well collector.

Step11: To form source and drain regions of PMOS and to make contact in P-base region the P-type
impurities are heavily doped.
• Step12: Then the entire surface is covered with the thick oxide layer.

• Step13: Through the thick oxide layer the cuts are patterned to form the metal contacts.
• Step14: The metal contacts are made through the cuts made on oxide layer and the terminals are
named as shown in the below figure.
Advantages of BiCMOS technology

• Analog amplifier design is facilitated and improved by using high impedance CMOS circuit as input and
remaining are realized by using bipolar transistors.
• BiCMOS is essentially vigorous to temperature and process variations offering good economical
considerations (high percentage of prime units) with less variability in electrical parameters.
• High load current sinking and sourcing can be provided by BiCMOS devices as per requirement.
• Since it is a grouping of bipolar and CMOS technologies we can use BJT if speed is a critical parameter and
we can use MOS if power is a critical parameter and it can drive high capacitance loads with reduced cycle
time.
• It has low power dissipation than bipolar technology alone.
• This technology found frequent applications in analog power managing circuits and amplifier circuits such as
BiCMOS amplifier.
• It is well appropriate for input/ouput intensive applications, offers flexible inputs/outputs (TTL, CMOS and
ECL).
• It has the advantage of improved speed performance compared to CMOS technology alone.
• Latch up invulnerability.
• It has the bidirectional capability (source and drain can be interchanged as per requirement).
Drawbacks of BiCMOS technology

• The fabrication process of this technology is comprised of both the CMOS and bipolar
technologies increasing the complexity.
• Due to increase in the complexity of the fabrication process, the cost of fabrication also
increases.
• As there are more devices, hence, less lithography.
Realization of bicmos:

• Bicmos technologies is broadly classified into three categories

1. Low-cost, medium speed,5-V digital
2. High performance, high cost, 5-V digital
3. Analog / digital
• The first two processes involves the addition of few extra mask sets to
the conventional cmos process
• The major difference between analog /digital & 5-V digital bicmos is
from operating voltages.
• Analog device has wide range of power supply(i.e., higherthan 10v)
Low-cost, medium speed,5-V digital:
• In this technology, there is addition of one extra mask existing n-well cmos process
• The extra mask level is for the formation of lightly doped p-regions at as p-base of bipolar transistor
• The n-well forms the collector regions of npn transistor
• Bipolar emitter, collector contact & nmos n+ source/ drain regions are formed using ion implantation
• The pmos p+ source/drain implant is used to create the base of contact for reducing base resistance R B
• This process is called as triple-diffused Bicmos(3D)
• The main drawback of 3D bipolar transistor is the large collector series resistance and for the n-
well collector, it is typically 2k ohms/sq.

• The large Rc value can causes internal debiasing of the base-collector junction at high currents,
and this debiasing reduces the drive current which can cause the gate delay to increase

• To reduce the Rc values, the transistor size can be increased.

• Such an approach, however, increases the collector and emitter junction capacitance, which
causes the drain-to-source current, Ids, from the cmos gate to drive the bipolar drivers.

• Optimizing the performance of the cmos gates can produce sufficiently large Ids values.
High performance, high cost, 5-V digital:

• In this technology, two basic apprpaches have been employed

1. Modification of a p-well CMOS process through the addition of three masking steps and
2. Modification of a twin-well CMOS process through the addition of three or four masking steps

P-well cmos process:

• The p-well cmos method process is as shown in figure
• It overcomes the high collector series resistance problem. Such is due to the insertion of a buried n+ layer
under the n-well.
• This heavily doped buried Layer is commonly employed in the bipolar only process to reduce collector
resistance.
• This buried layer is applied to the BICMOS processes, three key advantages can be realized:
1. Reduction in collector resistance, Rc
2. Lowering of CMOS latchup susceptibility
3. Better latchup immunity by using the n-epitaxial layer in place of p-epitaxial layer
• This process begins with deposition step, whereby a lightly doped n-epitaxial layer is deposited on a
p-substrate that has selectively formed n+ regions
• These n+ regions knowns as standard buried collectors, form the collector regions of the bipolar transistors
• The p-well is employed to provide bipolar junction–isolation among adjacent collectors
• The three extra masking steps to the baseline p-well CMOS process are used to form the n+ buried layer, the
collector deep n+ layer, and the p-base region
• Although the SBC process is simpler then the modified twin-well process, its device performance is slower.
• There are two reasons for this performance, the first is the limited packing density due to low p-substrate
doping level
• The low doping concentration demands a sufficiently wide collector-to-collector spacing to prevent punch
through from one bipolar collector to another.
• To have closer device spacing, the substrate doping level can be increased, but this change will raise the
collector-to-substrate capacitance
• Second, the counter doping of the n-epitaxial layer for isolating the n-well regions and to form p-wells for the
nmos device can raise
• Adding sufficient p-dopants to the n-epitaxial layer can cause not only processing problems but also
performance degradation to nmos due to mobility degradation.
Twin-well bicmos process:
• In this, the bipolar packing density can be improved by self-aligning buried p-layer to the buried n+ region as
shown in figure. Thereby tightening the isolation spacing between adjacent wells
• Then the spacing between adjoining collectors is significantly reduced, the collector-to-substrate sidewall
capacitance is increased
• This technique does not require for counter-doping of the n-type epitaxial layer
• By depositing a near intrinsic epitaxial layer instead of the n-type epitaxial layer, the doping level of
which is determined by the requirements of the bipolar and Pmos devices
• The self-aligned p- and n- wells are implanted into the thin intrinsic epitaxial layer, can be optimised
independently
• Another technology enchantment achieved in this technique is the use of an extra mask to realize
polysilicon emitter rather than the diffused emitter created during n+ source / drain formation
• The polysilicon emitters permit better bipolar performance because shallower emitters and narrower
base bandwidths can be achieved
• This enabling the reducing in transmit time and emitter-to-base parasitic capacitance (through
reduction of emitter-base junction area)
• The added process complexity can be reduced by concurrently forming the CMOS gates and bipolar
emitter using the same polysilicon layer
BICMOS MANUFACTURING AND INTEGRATION CONSIDERATIION

Consideration Of Cmos Device Structures

• The performance and reliability of cmos structures in bicmos circuits are the two most important
bicmos considerations
• The CMOS-intensive nature of the Bicmos process demands that the cmos transistors operate at high
speed because bipolar circuits cannot always be used in the critical speed path
• The twin well CMOS approach is the ‘choice’ well architecture for fabricating high performance
BICMOS structures because individual wells can be optimised separately by adjusting the doping
considerations
• Process design factors such as threshold voltage adjustment, drain design, and channel doping profiles
impose a significant impact on transistor performance and reliability
Threshold adjustment for CMOS devices:

• In mos ic applications , the Vt of mos device is the minimum gate voltage is necessary for turning ON
transistor
• It is crucial to establish a uniform and stable Vt . The factors affect Vt a given by

Where
=metal semiconductor work function
Qox= oxide layer charge density
Qb= depletion layer charge density
Cox= oxide capacitance per unit area
=surface potential
Where NA = Acceptor density
ni= intrinsic carrier concentration
K= boltsmanns constant
T=temperature in degree kelvin
q= electronic charge

is determined by the choice of gate conductor material

is depends on the substrate doping

QOX is reduced by improved oxidation method
QB can be adjusted by doping of substrate
Cox depends on the thickness and dielectric constant of the insulator

• As the dimensions of the gate are reduced, the threshold voltage of MOSFET becomes less ny the long
channel Vt
• When the channel length dimension, L is reduced <2um, the error become significant
• Vt usually decreased as L is reduced
• Reducing Vt with L and Vds in short channel device is critical since the enhancement mode FETs in CMOS
are generally designed to operate at Vt values of 0.6-0.8v
• In short channel MOSFETs, Vds is increased then Vt is decreased
• If magnitude of Vt reduces slightly, when Vgs=0v, the device may exhibit excessive leakage current
• Implanting boron, arsenic and phosphorous ions into the region under the gate oxide can adjust Vt
• Boron causes the positive shift in Vt, whereas arsenic and phosphorous implantation gives a negative shift
• In CMOS structures, the threshold voltages of the nmos and pmos devices can be adjusted to the desired
values by implanting a suitable amount of boron and phosphorous into the nmos and pmos channel regions
PRODUCTION OF GRADED-DRAIN STRUCTURE:

• The graded drain regions that help to minimize electric field distribution in the areas
• These approaches includes
1. using phosphorous instead of arsenic as the dopant of the source/ drain regions
2. Introducing fast diffusing phosphorous to an arsenic doped drain regions and driving the phosphorous
laterally ahead of the arsenic with a high-temperature diffusion step to create a step called double diffused
drain structure
3. Separating the highly doped n+ drain region from the gate edge using an “oxide spacer” to create a so-called
lightly doped drain structure
Phosphorous-drain structure:

• The method to realize graded-drain regions from conventional MOSFET device is replacing arsenic
with phosphorous as the source/drain donor impurity. This structure is known as phosphorous-drain
structure.
• The phosphorous dopants that diffuse faster than arsenic provide additional lateral length to the drain
dopant profile and widen the depletion region of the drain-channel junction. These diffusion reduces
the maximum lateral electric field strength E ymax.
• The reduction in Eymax is due to both the graded phosphorous diffusion profile and the much deeper
source/drain junction depth
• Because of the deep source/drain junction, the short channel effects are much more difficult to
suppress
• This method is not suitable for nMOSFETs with gate lengths smaller than about 1.3um
Double Diffused Drain:

• In this technique, both arsenic & phosphorous are simultaneously employed in the form of drain rather
than using the single Phosphorous-drain structure, which is adequate for alleviating hot carrier reliability
problems
• Lateral encroachment into the MOSFET channel is now excessive, hence the improvement in hot carrier
reliability
• This technique uses two separate implants at the same source/drain regions: a medium Phosphorous dose
is introduced first prior to implanting the heavier arsenic dose
• Both dopants are implanted after the sidewall spacer formation and are introduced at 0 tilt angle
• After the implant steps, a high temperature anneal step is used to diffuse these dopants to form the DDD
as shown in fig.
• Because Phosphorous diffuses faster than arsenic, it is driven farther under the gate edge and around the
drain periphery creates a less abrupt concentration gradient for the drain
• A typical impurity distribution along the channel direction of a DDD MOSFET is given below figure
LIGHTLY –DOPED DRAIN:
• The LDD structure was first described in 1980 by Ogura et.al
• The structure involves two drain-implant steps where one is self aligned to the gate electrode and other is
self-aligned to the oxide sidewall spacer of the gate electrode
• The Phosphorous dopant is implanted before the formation of the oxide sidewall spacer and upon the spacer
formation where heavily doped source/drain impurity is implanted
• The purpose of the first implant dose is to produce a lightly doped section of the drain at the edge near the
channel as shown in fig.
• In this structure, 30-40% reduction in Eymax can be achieved
• This reduction can contribute significantly to the improvement of hot carrier reliability
• The LDD requires an additional mask for the LDD source/drain implant, it offers better control
of the electric field over the channel length and the device isolation
• The variation in the sidewall oxide thickness of graded-drain structures affects the overall
electric gate length
• The LDD technique is able to offer better isolation because of its ability of manufacturing
shallower heavily doped source/drain junction depth
• This further improves on the short-channel performance and eliminate the need for a deep punch
through implant
RETROGRADE WELL:

• "As semiconductors become more complex and transistors become smaller and smaller, power consumption
and heat have become limiting factors to the continued pace of chip design and manufacturing.
• As millions, or even billions, of smaller and faster transistors get packed on to a single chip the size of a
thumbnail, power consumption and the amount of heat generated in the processor core becomes a significant
technical challenge.
• In particular, as chip densities increase, off-state current leakage requires more power and generates more
heat, and may present a limit to chip size and integration.

One technique for reducing off-state leakage current is to form a well of dopant in the channel between the
source and drain regions of the transistor.
• For example, in an NMOS device, boron may be implanted into the channel using halo, or pocket, implant
methods.
• Similarly, in a PMOS device, phosphorus may be implanted into the channel using such implant methods.
• During the source drain anneal, the implanted boron (in an NMOS device) or phosphorus (in a PMOS
device) diffuses throughout the channel to form a well having a relatively uniform concentration of boron or
phosphorus for some depth below the gate.
• Such a well(Retrograde Well) affects the resistance of the channel between the source and drain such that
off-state leakage current (in other words, leakage current between the source and drain when the transistor is
off) is reduced"
PUNCH THROUGH IN SHORT CHANNEL MOSFETS:

• The punch through mechanism is described as reverse bias applied to drain, which results into extended
depletion region.
• The two depletion regions of drain and source therefore are inter sectioned with each other, and this results
into "one" depletion region, and flow of leakage current and consequently breakdown of MOSFET.
• When the drain is at a high enough voltage with respect to the source, the depletion region around the drain
may extend to the source, thus causing current to flow irrespective of the gate voltage( i.e., even if itis zero).
This is known as a punch through condition.
PROCESS CONSIDERATION FOR BIPOLAR TRANSISTORS:

To realize high performance BICMOS technologies, considerable care must be taken when designing the
base, emitter and collector.

DESIGN CONSIDERATION FOR BASE:

To realize high performance BICMOS structure the bipolar transistor most be
 high unity gain cut-off frequency ft
 Small parasitic capacitance, CBE, CBC,CEC.
• To allow for maximum ft , the base width must be narrow as possible
• This can be employed ion Implantation, coupled with the minimum thermal cycles
• The base profile should be optimized to prevent collector-emitter punch through as well as maximum emitter-
base breakdown voltage
• The decreases in width of the base region causes an increase in the base series resistance, hence degrading the
device characteristics
• Then reducing the spacing between the extrinsic base and emitter , self aligned schemes can be utilized, to
lower the base resistance
• Self aligned transistors have smaller parasitic areas, allowing reduced parasitic capacitances and enhanced
speed performance
Design consideration for emitter:
• The emitter of the bipolar transistor can be formed using several methods
 directly ion implanted emitter
 Single or double level polisicon technique
• Directly ion implanted emitter approach cannot be scaled for high performance applications, it can be used if
ft <8Ghz
• The single level polysilicon is as shown in fig. Uses the same poly silicon layer to form the emitter and the
mos transistor gate
• The buried layer and deep sink is used for the process to help to
reduce the collector-substrate capacitance
• The polysilicon has employed achieve well-controlled emitter and also facilitate the formation of
shallow base for the enhancement emitter efficiency
• The emitter is not self aligned. Two problems are occur
 Encroachment of the extrinsic base at the emitter region
it arises because of heavy p+ doped extrinsic base region
 Substrate exposure during emitter poly etch
this happens the emitter opening silicon substrate exposure during emitter operation, etching of silicon
substrate, which may lead to device shorting during salicidation

Double level polysilicon process

• In this, 1st level p+ polysilicon layer used to form the base electrode
can also employed to form the low- sheet resistance resistor
• The 1st level p+ polysilicon layer will form the polysilicon gates of the
cmos devices
• The 2nd level of polysilicon layer forms the emitter of the bipolar
transistor, which is self aligned to the extrinsic base.
• Then the ft of 16GHz have been fabricated using this double layer
emitter approach.
Design consideration for collector:
• When a high capacitive load is to be drive by the BICMOS circuits, the collector resistance of the bipolar is
critical because its determines the overall delay of the circuit
• When the collector current is increased ,the high collector resistance can bring the transistor in saturation, and
the holes are induced to the substrate then the latch up can be Induced
• To achieve the high performance BICMOS the collector resistance must be reduced
• The n+ silicon plug is used to minimize the collector series
resistance
• To presence of the lightly doped n- well between the collector
contact and buried n+
layer causes very high collector resistance
• To reduce the collector resistance , a deep n+ contact diffusion
(plug or sink) can be employed
• The dis adv of these section has the collector-to-base spacing
ISOLATION ON BICMOS:
Isolation: vlsi consists od several active and passive components interconnected within a monolithic block of
semiconductor material
Each component must be electrically separated from each other to aloe design flexibility
Why it is required:
• To prevent the undesired conducting paths
• To avoid creation of inversion layers outside the channel
• To reduce the leakage currents
ISOLATION IN BIPOLAR TRANSISTORS
Junction transistor:
• The method of isolation is most compatible with the IC processing, that is, one extra processing step, other
than required to fabricate IC, is required in isolation.
• Basically the method involves producing islands of n- type material surrounded by p-type material.
Components are then fabricated in different n-type islands.
• The p-type material surrounding the islands is given the most negative p potential with respect to all parts of the
wafer, thus each island and hence component is electrically isolated from the others by back-to-back diodes. The
process step for p-n junction isolation are explained below:
One begins with the p-type substrate on which n-epitaxial layer is grown.
If the component to be fabricated is transistor, then buried layer have to be formed before growing epi-layer. Figure
[a] shows epi-layer growth over substrate without buried layer.
The epi-layer is then covered with SiO2 layer.
A p-type diffusion is now performed from the surface of the wafer.
Since this is to be performed in selected areas, an isolation mask is prepared prior to this diffusion.
A long drive-in time is required for p-type diffusion so that the acceptor concentration is greater than the epi-layer
donor concentration throughout the region of epi-layer.
Thus the portion of wafer at the location of isolation diffusion is changed to p-type from the surface of wafer to the
substrate.
This is shown in the figure [b]. In other words, the substrate is extended toward the surface and acts as an isolation
wall.
This isolation wall causes the formation of p-n junction everywhere around the n-type islands except at the surface.
• If the substrate is connected to a voltage which is more negative than any of the n-region voltages, the diodes
shown will be reversed biased and negligible current will flow.
• Thus isolation is achieved since any reverse biased p-n junction is associated with a depletion capacitance;
this will have parasitic effect associated with junction, particularly, at high frequencies.
• The main disadvantage of p-n junction isolations is as below:
1. The time required for such isolation technique is considerably longer due to diffusion
time taken, which is longer than any of other diffusions.
2. Lateral diffusion is significant due to longer time taken by isolation diffusion, hence
considerable clearance must be used for isolation regions.
3. Isolation diffusion takes an area of the wafer surface which is significant portion of the
chip area. From component density consideration, this area is wasted.
4. P-N junction isolation method introduces significant parasitic capacitance which
degrades circuit performance. The parasitic capacitance is introduced by isolation
sidewall and bottom epitaxial substrate junction.
OXIDE ISOLATION:
• Isolation can also be obtained by the formation of individual tubs of active material, which are lined with an
oxide layer.
The process is as follows:
1. An n-type silicon slice is masked with SiO2.
2. Anisotropic etching is done to get V-shaped grooves.
3. Highly doped n layer is diffused across entire slice to provide low resistance ohmic contact.
4. Thermal oxide is grown over wafer which act as isolation between single crystal and subsequent
polycrystalline silicon which is next deposited to thickness of 250-500 μm.
5. Single crystal side of slice is thinned resulting in a structure shown in figure. Mechanical polishing followed
by chemical etching of etch stop layer is commonly used.
6. Resulting slice consist of a series of tubs of single crystal silicon, isolated from each other by sio2.
7. Each tub is lines with n+  layer which provides collector connection with a low paretic resistance.
ISOLATION IN MOS TRANSISTORS:

LOCOS:
• Local Oxidation of Silicon (LOCOS) is the traditional isolation technique.
• At first a very thin silicon oxide layer is grown on the wafer, the so-called pad oxide.
• Then a layer of silicon nitride is deposited which is used as an oxide barrier.
• The pattern transfer is performed by photolithography.
• After lithography the pattern is etched into the nitride. The result is the nitride mask as shown
in Figure, which defines the active areas for the oxidation process.
• The next step is the main part of the LOCOS process, the growth of the thermal oxide. After the
oxidation process is finished, the last step is the removal of the nitride layer.
• The main drawback of this technique is the so-called bird's beak effect and the surface area
which is lost to this encroachment.
• The advantages of LOCOS fabrication are the simple process flow and the high oxide quality,
because the whole LOCOS structure is thermally grown.
Trench Isolation:

Shallow trench isolation:

• Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which
prevents electric current leakage between adjacent semiconductor device components.
• STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older
• CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.
• The Shallow Trench Isolation (STI) is the preferred isolation technique for the sub-0.5 μm technology,
because it completely avoids the bird's beak shape characteristic.
• With its zero oxide field encroachment STI is more suitable for the increased density requirements, because it
allows forming of smaller isolation regions.
• The STI process starts in the same way as the LOCOS process. The first difference compared to
• LOCOS is that a shallow trench is etched into the silicon substrate, as shown in Figure.(a)
• After underetching of the oxide pad, also a thermal oxide in the trench is grown, the so-called liner oxide
(Figure c).
• But unlike with LOCOS, the thermal oxidation process is stopped after the formation of a thin oxide layer, and the
rest of the trench is filled with a deposited oxide (Figure d).
• Next, the excessive (deposited) oxide is removed with chemical mechanical planarization. At last the nitride mask is
also removed. The price for saving space with STI is the larger number of different process steps.
Deep trench isolation:
• It uses the trenches of fixed width, typically 0.18 to 1 μm in width and 2 to 5 m in width and 2 to 5 μm in
depth. Smaller trench widths are particularly attractive for memory application.
• It finds application in CMOS image sensors (used in camera).
• The process is fabricated by starting from a standard LOCOS structure.
• After nitride patterning, the trenches are etched. Trench is typically done by simultaneously depositing sio2
while etching silicon an isotropically.
• This creates small cusp of  sio2 at the top of the trench. The thickness of this cusp increases with time and
create desired taper.
• The walls cannot undercut the mask and must result in rounded bottom.
• Then a field implant is done. The implant is followed by a thin local oxidation.
• Finally a layer of polysilicon is deposited and etched back. If polysilicon is thick enough it will fill the
groove. Second thermal oxidation can be used to complete the process by oxidizing the upper part of
polysilicon in groove.
Thank
you