ADVANCED MICRO CONTROLLER

SYLLABUS

Unit I –AVR Microcontroller

Overview of The AVR Family, AVR Architecture, General
Purpose Registers in AVR, DataMemory, Status Register,
Data Format and Directives.
Introduction to AVR Assembly Programming, Assembling
an AVR Program, The Program Counter and Program ROM
Space in the AVR, RISC Architecture in the AVR.
OVERVIEW OF AVR
AVR FAMILY OVERVIEW
• Mega AVR
Program memory: 4K-256K
Package:28-100 pins
Extensive peripheral set, extended instruction set.
AVR FAMILY OVERVIEW
• Tiny AVR
Program memory: 1K-8K
Package:8-28 pins
limited peripheral set and instruction set.
AVR FAMILY OVERVIEW
• Special purpose AVR
GPRs in the AVR
LDI
Conti…
AVR Data Memory
Conti…
AVR STATUS REGISTER
AVR DATA FORMAT AND DIRECTIVES
• Data format Representation:
Hex Numbers
Decimal numbers
 Binary numbers
ASCII characters
Assembler Directives
• .EQU
• .ORG
• .INCLUDE
Structure OF AVR Assembly Language
Assembling AVR program
Sample program
List file
 • PC
• address of the next instruction to be
executed.
• As the CPU fetches the opcode from
program ROM, the PC is incremented
PROGRAM by 1, which points to the next
instruction.

COUNTER(P • Size of PC—(14 bit to 22-bit).

C) IN AVR • In AVR microcontrollers, each flash

memory location is 2-bytes wide.
• e.g. ATMega32---> ROM size is 32KB
 organized as 16KB x 2B.
ROM memory map in AVR family
Where the AVR
wakes up when it is
powered up?
Placing code in program ROM
Executing a program instruction-by-
instruction
ROM width in the AVR

AVR is word-addressable.
Harvard
Architecture in
the AVR
Instruction size of the AVR
ADD INSTUCTION FORMATION
FEATURES
• RISC processors have a fixed instruction size.
• RISC processors have a large number of registers.
• RISC processors have small instruction set.
• >95% instructions are executed with only single clock cycle.
• RISC processors have separate buses for program and data.
• In RISC, there are 4 sets of buses-
• 1) a set of data buses for carrying data (operands) in and out of CPU.
• 2) a set of address buses for accessing the data.
• 3) a set of buses to carry the opcodes.
• 4) a set of address buses to access the opcodes.
FEATURES
• RISC uses LOAD/STORE architecture.
• RISC instructions are implemented using hardwire method.
Hardwiring of RISC instructions takes no more than 10% of the
transistors.