Ch 8 Advance CMOS Logic

Mirror Circuits
Pseudo-nMOS
Tri-State Circuits
Clocked CMOS
Dynamic CMOS Logic Circuits
Dual-Rail Logic Networks
 Mirror Circuit
• Faster and has uniform layout.
• Has shorter rise and fall times

Elmore time constant:  x  Cout 2 Rx   C x Rx

Approximating the output voltages, as t r  2.2 p
being exponential gives the rise and fall
t f  2.2 n
time’s expressions :
Every path between the output and a power supply
rail consists of two resistors and a parasitic inter-
FET capacitor.
 Pseudo-NMOS

For N inputs, a pseudo-nMOS logic gate requires (N + 1) FETs

But Standard N-input CMOS gates use 2N FETs.
 PFET is always biased ON.
VOL can never achieve the
ideal value of 0V. This can
be overcome by adjusting
the size of PFET.
n
VOL depends on the ratio  p
With the increase in the device
ratio, VOL will decrease.

p
n
2
2VDD  VTn VOL  VOL  
2

2
 VDD  VTp2

VOL  VDD  VTn   VDD  VTn  

2 n
p
 VDD  VTp 
2
Pseudo NMOS is Ratio-less logic
i.e., the transistor widths must be chosen properly,
i.e., The pull-up transistor must be chosen wide enough to
conduct a multiple of the n-block's leakage and narrow
enough so that the n-block can still pull down the output
safely.

Advantage of pseudo-NMOS logic are:

its high speed and
low transistor count.

Disadvantage is
static power consumption of the pull-up transistor as well as
the reduced output voltage swing and gain, which makes the
gate more susceptible to noise.
And also increased cost.
 Tri-State Circuits
Uses additional input enable.
M1 and M2 are tristating devices
Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
 “Static CMOS Logic”

“Here output is logic function of inputs,

and,
given stable inputs, does not change over
time”.

• Full rail-to-rail swing; high noise margins

• Logic levels not dependent upon relative
device sizes
• Always a path to Vdd or Gnd in steady
state; low
output impedance
• Extremely high input resistance; nearly
zero
steady-state input current
• No direct path steady state between power
and
ground; no static power dissipation
Clocked CMOS (C2MOS)

1
f 
T
non  overlapping t  t   0
t   VDD  t 
M1and M2 are controlled by the clock signals  and bar.
When  = 1, both M1 and M2 are active,
Circuit degenerates to a standard static logic gate
Output f(a,b,c) is valid during this time, establishing the voltage Vout on
the output capacitance Cout.
When the clock changes to a value  = 0, both M1 and M2 are in cutoff, so
that the output is in high-impedance state Hi-Z.
Advantages

• Clock controls the entire operation of the logic gate.

Hence we can synchronize the data flow
• New group of data bits enter the network during every clock
cycle .

Disadvantages

• Output node cannot hold the charge on Vout for a very long
time due to charge leakage.
• A limit on allowable clock frequency.
• Can operate at lower frequency range only.
 dV  IL 
I L  iout  in  i p  C out V t   V1   t
dt  C out 
 IL   C out 
hold time V t h   V1   t h  V x t h   V1  V x 
 C out   IL 
Dynamic Logic
 Precharge clock to charge the capacitance
Evaluate clock to discharge the capacitance depending on condition of
logic inputs.
In dynamic CMOS logic a single clock  can be used to accomplish
both the pre-charge and evaluation operations.

When  is low, PMOS pre-charge transistor Mp charges the capacitor

Cout to charge to a voltage of Vout = Vdd, since it remains in its linear region
during final pre-charge. During this time the logic inputs A1 … B2 are active;
however, since Me is off, no charge will be lost from Vout.
When  goes high again, Mp is turned off and the NMOS evaluate
transistor Me is turned on, allowing for Vout to be selectively discharged to
GND depending on the logic inputs, i.e. If A1 … B2 inputs are such that a
conducting path exists between Vout and Me, then Cout will discharge through
the logic array and Me; this gives the final result of Vout = 0 V, corresponding
to the output of f = 1. Otherwise, Vout remains at Vdd.
An Example of Dynamic CMOS Logic.
 Dual-rail Logic Networks

Single-rail logic circuits have the value of the variable as either 0 or 1

only.
Dual-rail networks, both the variable x and its complement xbar are
used to form the difference fx = (x – xbar).
 Using the quantity fx provides an increase in the
switching speed, almost twice as fast as the single-rail
logic circuit.

Complicating factor in dual-rail logic networks is

the increase in the circuit complexity and wiring overhead.

Circuits are more complicated and can be tricky to

deal with.

Their switching speed makes them worth studying.

 Bi-CMOS Logic

• It combines Bipolar and CMOS transistors onto a single

integrated circuit.

• Hence advantages of both can be utilized.

•Advantages of CMOS over Bipolar are: Power dissipation,

Noise margin, packing density, the ability to integrate large
complex functions with high yields.

•Advantages of Bipolar over CMOS are: Switching speed,

Currents drive per unit area, Noise performance, Analog
capability, Input/output speed.
 The overall advantages of BiCMOS Technology are:
Improved speed over CMOS, Lower power dissipation than
Bipolar, Flexible input/outputs, High performance analog,
Latch up immunity.

An Example
Vdd  

Vin T2  
T4  

Vout

T1  
T3  
CL  
 Disadvantage is the greater process complexity
compared to CMOS.

However, as CMOS complexity has increased, the

percentage difference between CMOS and BiCMOS mask
steps has decreased.
 References

1. Introduction to VLSI Circuits & Systems By John.P.Uyemura.

2. Basic VLSI Design (Third Edition) By Douglas.A.Pucknell ,

Kamaran Eshraghian.