RISC vs CISC

INTRODUCTION

 RISC – Reduced Instruction Set Computer

 RISC is a type of microprocessor architecture that utilizes
 a small, highly-optimized set of instructions
 rather than a more specialized set of instructions.

The main alternative for RISC is CISC ,which stands for

complex instruction set computer.
CISC is the older approach, that came about to maximize
performance of earlier computer’s. Where instructions were
executed sequentially.
BACKGROUND AND HISTORY

 RISC approach developed as a result of development in 1970’s

- increase in memory size
- decrease in cost
- advanced compilers
 In late 1970’s IBM was the first to start.
 In 1980 , David Patterson ,began the project that gives this
approach RISC.
 After some years ,Stanford MIPS was developed,
CHARACTERSTICS OF RISC

 Simplified instructions , taking 1 clock cycle.

 Large no. of general purpose registers.
 Circuit is much simpler.
 Fast to decode.
 Fast to execute.
Pipelining- fetching of next instruction while previous
instruction executes.
 CISC VS.RISC
1. The CISC approach attempts to
minimize the number of
instructions per program,
sacrificing the number of cycles
per instruction.
2. Complex Instructions.
3. Many operations in single
instruction.
4. Code size is smaller but
complicated.
Example:
ADD AX,[BX + SI + 600H]
1. RISC does the opposite,
reducing the cycles per
instruction at the cost of the
number of instructions per
program.
2. Simpler or reduced instructions.
3. One operation in one instruction.
4. Code size is larger but simpler.
Example:
LOAD R1, addresss1
LOAD R2, address2
ADD R1, R2
STORE address1, R1
REGISTERS AND ADDRESSING MODE
CISC
1. Fewer register.
2. These registers are designed
for special purposes.
3. CISC designs provide a
large number of addressing
modes
RISC
1. Large number of registers.
2. Here registers are identical so
any register can be used for any
purpose.
3. RISC designs have single
addressing modes.
 CISC
1. Slower to execute.
2. Difficult to decode.
3. Instruction size varies in
different instructions.
4. Complex circuit design.
RISC
1. Faster execution.
2. Easy to decode.
3. Same instruction size in every
instructions.
4. Circuit design is simpler.
RISC microprocessors CISC processors are the
are Alpha, ARC, ARM, System/360, VAX, PDP-
AVR, MIPS, PA-RISC, 11, Motorola 68000
PICPower family, AMD, and Intel
Architecture, and x86 CPUs
SPARC.
Characteristics of RISC
• Relatively few instructions.
• Relatively few addressing modes.
• Memory access limited to load and store instructions.
• All operations are done within the registers of the CPU.
• Fixed-length, easily decoded instruction format.
• Single-cycle instruction execution.
• Hardwired rather than microprogrammed control.
• A relatively large number of registers in the processor unit.
• Use of overlapped register windows to speed-up procedure call and return.
• Efficient instruction pipeline.
• Compiler support for efficient translation of high-level language programs into machine
language programs.
Characteristics of CISC
• A larger number of instructions – typically from 100 to 250
instructions
• Some instructions that perform specialized tasks and are used
infrequently
• A large variety of addressing modes – typically from 5 to 20
different modes
• Variable-length instruction formats
• Instructions that manipulate operands in memory
RISC APPLICATIONS
HIGHEND RISC &
LOW END & MOBILE
SUPERCOMPUTING
SYSTEM
•MIPS
•ARM ARCHITECTURE used in embedded system in routers,
Android based systems/ Apple used by Digital Equipment
iPhone/Nintendo GBA etc. Corporation etc.
• MIPS line •IBM’S Power Architecture
in PlayStations, Nintendo 64 etc. In many IBM’s supercomputers,
workstations etc.
• Atmel AVR
•Alpha
Xbox handheld controllers to
BMW car In Single-board computers,
Servers & Supercomputers from
Digital Equivalent Cooperation
etc.
ARM BASED
PRODUCTS.
ARM Architecture
• Developed by Advanced
RISC Machines (ARM).
• ARM makes 32-bit & 64-bit
RISC
multi-core processors.
• Features of ARM
architecture:
 A load/store architecture
 An orthogonal instruction set.
 Fixed instruction width
 Mostly single clock-
cycle execution.
 Enhanced power-saving
design.
 Hardware virtualization
supports.