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Switching Theory and Logic Circuits
Switching Theory and Logic Circuits
LOGIC CIRCUITS
COURSE OBJECTIVES
1. To understand the concepts and techniques associated with the
number systems and codes
2. To understand the simplification methods (Boolean algebra &
postulates, k-map method and tabular method) to simplify the
given Boolean function.
3. To understand the fundamentals of digital logic and to design
various combinational and sequential circuits.
4. To understand the concepts of programmable
logic devices(PLDs)
5. To understand formal procedure for the analysis and design of
synchronous and asynchronous sequential logic
COURSE OUTCOMES
After completion of the course the student will be able to
1. Understand the concepts and techniques of number systems
and codes in representing numerical values in various number
systems and perform number conversions between different
number systems and codes.
2. Apply the simplification methods to simplify the given Boolean
function (Boolean algebra, k-map and Tabular method).
3. Implement given Boolean function using logic gates, MSI
circuits and/ or PLD’s.
COURSE OUTCOMES
After completion of the course the student will be able to
4. Design and analyze various combinational circuits like
decoders, encoders, multiplexers, and de-
multiplexers, arithmetic circuits (half adder, full adder, multiplier
etc).
5. Design and analyze various sequential circuits like flip-
flops, registers, counters etc.
6. Analyze and Design synchronous and asynchronous sequential
circuits.
UNIT-I
Introductory Concepts
(Number systems, Base conversions)
Digital Systems
● Groups of
four bits are
Understanding Binary Numbers
Octal
(base 8)
Decimal Binary
(base 10) (base 2)
Hexadecimal
(base 16)
Convert an Integer from Decimal to Another Base
MSB
Convert a Fraction from Decimal to Another Base
MSB
The Growth of Binary Numbers
n 2n n 2n
0 20=1 8 28=256
1 21=2 9 29=512
2 22=4 10 210=1024 Kilo
3 23=8 11 211=2048
4 24=16 12 212=4096
5 25=32 20 220=1M Mega
175/8 = 21 + 7 a0 = 7
21/8 = 2 + 5 a1 = 5
2/8 = 0 + 2 a2 = 2
● Conversion is easy!
Determine the 4-bit binary value for each hex digit
● Note that there are 16 different values of four bits
● Easier to read and write in hexadecimal
● Representations are equivalent!
1 1 1 1 1 1 carries
1 1 1 1 0 1 = 61
+ 1 0 1 1 1 = 23
1 0 1 0 1 0 0 = 84
Binary Subtraction
1 10
0 10 10 0 0 10 borrows
1 0 0 1 1 0 1 = 77
- 1 0 1 1 1 = 23
1 1 0 1 1 0 = 54
Binary Multiplication
1 0 1 1 1
X 1 0 1 0
0 0 0 0 0
1 0 1 1 1
0 0 0 0 0
1 0 1 1 1
1 1 1 0 0 1 1 0
Summary
000011002 = 1210
100011002 =
−1210
000011002 = 1210
111100112 = −1210
Ignore
Carry
2’s Complement Subtraction
Carry 1 01000
● Discarding the carry bit, the sign bit is seen to be
zero, indicating a positive result
Indeed: (01000)2 = +(8)10
2’s Complement Subtraction
Carry 0 11001
● Here, there is no carry bit and the sign bit is 1.
This indicates a negative result, which is what we
expect: (11001)2 = – (7)10
Summary
● ASCII Codes
● A – Z (26 codes), a – z (26 codes)
● 0 – 9 (10 codes), others (@#$%^&*….)
● Transmission susceptible to noise
● Typical transmission rates (1500 Kbps, 56.6 Kbps)
● How to keep data transmission accurate?
Parity Codes
P Information Bits
1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1
Added even parity bit Added odd parity bit
Parity Code Example
Binary Cell
Register Transfer
Register A Register B
Digital Logic
Circuits
Register C
Transfer of Information
● We need processing
● We need storage
● We need communication
● Analysis problem:
● An input of 0 is inverted to a 1 A Y
● An input of 1 is inverted to a 0 0 1
1 0
A Y
Input Output
Symbol
The AND Gate
A A B
Y
B
The OR Gate
● This is an OR gate
A B Y
● If either of the two
0 0 0
input signals is 0 1 1
asserted, or both of 1 0 1
them are, the output 1 1 1
will be asserted
A
A
Y B
B
Describing Circuit Functionality: Waveforms
3 Input OR Gate
Ordering Boolean Functions
● How to interpret A B + C?
Is it A B ORed with C ?
Is it A ANDed with B + C ?
● Order of precedence for Boolean algebra: AND
before OR
● Note that parentheses are needed here:
Boolean Algebra
● Commutative Property:
For every ‘a’ and ‘b’ in K,
a+b=b+a
a•b=b•a
● Associative Property:
For every ‘a’, ‘b’, and ‘c’ in K,
a + (b + c) = (a + b) + c
a • (b • c) = (a • b) • c
Distributivity of the Operators and Complements
● Distributive Property:
For every ‘a’, ‘b’, and ‘c’ in K,
a+(b•c)=(a+b)•(a+c)
a•(b+c)=(a•b)+(a•c)
a)
Summary
x y z xy yz G
0 0 0 0 0 0
0 0 1 0 0 0 x xy
0 1 0 0 0 0 y
0 1 1 0 1 1 G = xy +yz
1 0 0 0 0 0 z
yz
1 0 1 0 0 0
1 1 0 1 0 1 Ho
w to transit between an
1 1 1 1 1 1 equation, a
circuit, and a truth table?
Representation Conversion
Truth
Tabl
e
Truth Table to Expression
x y z G
0 0 0 0 Any Boolean Expression can be
0 0 1 0 represented in sum of products form!
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
xyz + xyz’ + x’yz
Equivalent Representations of Circuits
x y z
G = xyz + xyz’ + x’yz
Reducing Boolean Expressions
x y z
G = xyz + xyz’ + x’yz = xy + yz
Minterms and Maxterms
x y z Minterm x y z Maxterm
0 0 0 x’y’z’ m0 0 0 0 x+y+z M0
0 0 1 x’y’z m1 0 0 1 x+y+z’ M1
… …
1 0 0 xy’z’ m4 1 0 0 x’+y+z M4
… …
1 1 1 xyz m7 1 1 1 x’+y’+z’ M7
Representing Functions with Minterms
x y z G
0 0 0 0
G = xyz + xyz’ + x’yz
0 0 1 0
0 1 0 0
0 1 1 1 G = m7 + m6 + m3 =
1 0 0 0
1 0 1 0 Σ(3, 6, 7)
1 1 0 1
1 1 1 1
Complementing Functions
x y z G G’
0 0 0 0 1 G = xyz + xyz’ + x’yz
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 G’ = (xyz + xyz’ + x’yz)’ =
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0 ?
1 1 1 1 0
Can we find a simpler representation?
Complementing Functions
x y z F
0 0 0 0
0 0 1 0
x
0 1 0 0
0 1 1 0 y F = x(y+z’)
y+z’
1 0 0 1 z’
z
1 0 1 0
1 1 0 1
1 1 1 1 F = x(y+z’)
Logic functions of N variables
● Each truth table represents one possible function
(AND, OR … etc)
● If there are N inputs, there are 22N
● For example, if N is 2 then there are 16 possible
truth tables
● So far, we have defined 2 of these functions
● 14 more are possible
x y G
● Why consider new functions?
0 0 0
● Cheaper hardware, more flexibility 0 1 0
1 0 0
1 1 1
The NAND Gate
NOT Gate A
Y
B
A AND Gate
Y
B
OR Gate
The NOR Gate
B 1 0 0
Y=A+ 1 1 0
B
Functionally Complete Gates
NOT Gate A
B Y
A OR Gate
Y
B
AND Gate
The XOR Gate (Exclusive-OR)
A
Y = A B Y
B
The XNOR Gate
a)
Example
DeMorgan’s Theorem
Interpretation of the two OR gate symbols
DeMorgan’s Theorem
Summary
x y F
y
x 0 1 0 0 1
0 1 1 0 1 1
y
1 0 0 1 0 0
y
x 0 1 1 1 0
0 x’y’ x’y
x
1 xy’ xy F = Σ(m0,m 1) = x’y + x’y’
Karnaugh Maps
bc bc
a 00 01 11 10 a 00 01 11 10
0 0 0 1 0 0 0 0 1 1
1 0 1 1 1 1 0 0 1 1
cout = ac+bc + f=b
ab
A B Cin S Cout
Cin 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0 How to use a Karnaugh
A 0 1 1 0 1
Adder S Map instead of the
1 0 0 1 0
B 1 0 1 0 1 Algebraic simplification?
1 1 0 0 1
1 1 1 1 1
Cout
+
B B
C
A 11 10
00 01
0 Now we have to cover all the 1s in the
0 0 1 0 Karnaugh Map using the largest
A 1 rectangles and as few rectangles
0 1 1 1 as we can.
C Cout = BCin + AB + ACin
B
BC
A 00 01 11 10
0
Now we have to cover all the 1s in the
0 1 0 1 Karnaugh Map using the largest
1
rectangles and as few rectangles
A 1 0 1 0 as we can.
C S = A B’ C’in + A’B’Cin + A B Cin+A’ BC’in
No Possible Reduction!
Karnaugh Map for S
Summary
1 0 1 1
0 1 1 1
0 0 1 1
1 0 1 1
F = C + A’BD + B’D’
Design Examples
K-map for LT
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
F = A’C + A’B’D +
B’CD
Design Examples
K-map for EQ
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
K-map for GT
0 0 0 0
1 0 0 0
1 1 0 1
1 1 0 0
1 0 0 0
EQ
EQ
0 1 0 0
0 0 1 0
0 0 0 1
B
Karnaugh Maps: Don’t Cares
1
+
0 0 0 0
A 1 0 0 1 1
10 0 1 0 0
1 0 1 0 0
D 1 0 1 1 0
1 1 0 0 X
1 1 0 1 X
1 1 1 0 0
Without don’t cares 1 1 1 1 0
F=A’D + B’C’D
A'D
ca r e
w W i t h don’t
F=A’D + C ’D cares
Don’t Care Conditions
● In some situations, we don’t care about the value of a
function for certain combinations of the variables
● these combinations may be impossible in certain contexts
● or the value of the function may not matter when the
combinations occur
● In such situations we say the function is incompletely
specified and there are multiple (completely
specified) logic functions that can be used in the
design
● so we can select a function that gives the simplest circuit
CD
00 01 11 10
AB
00 0 1 0
0 x
01 x x F=ACD+B+AC
11 1 1 1 x
1
10 x 0 1
1
00 01 11 10
ABC D
00 0 1 0
0 x
01 x x
11 1 1 1 x
1 F= ABCD + B C +AC+ABC
10 x 0 1
1
Alternative covering:
Karnaugh Maps: Product of Sums
F(A,B,C,D) = (2,3,9,11,13) + d(6,14)
CD
AB 00 01 11 10
00 0 0 1 1
01 0 0 0 x
11 0 1 0 x
00 01 11
10 0 1 1 0
CD
AB 00 01 11 10
00 1 1 0 0
01 1 1 1 x
11 1 0 1 x
00 01 11
10 1 0 0 1
G = AD‘ + A‘C‘ + BC
Karnaugh Maps: Product of Sums
F(A,B,C,D) = (2,3,9,11,13) + d(6,14)
CD
AB 00 01 11 10
00 0 0 1 1
01 0 0 0 x
11 0 1 0 x
00 01 11
10 0 1 1
0
((AA++CC))(A+
’ D)
Prime Implicants
CD C
AB 00 01 11 10
00 0 X 1 0 A’D, AC, A‘BC‘, CD, BC'D'
01 1 1 1 0
B essential
11 1 0 1 1
A minimum cover: AC + A‘D + BC'D'
10 0 0 1 1
D
Examples to Illustrate Terms
CD
AB 5 prime implicants:
C
BD, ABC, AC'D, A'BC'‘,
00 01 A'CD
11 10 B
11
A 00 0 0
10 1 0
minimum cover: 4 essential implicants
01 1D 1
1 0
0 1 1 1
0 1 0 0
Summary
DeMorgan’s Law:
(a + b)’ = a’ b’ (a b)’ = a’ + b’
a+b ab =a +
b
=
● Sum-of-products
● AND gates to form product terms
(minterms)
● OR gate to form sum
● Product-of-sums
● OR gates to form sum terms
(maxterms)
● AND gates to form product
Two-level Logic using NAND Gates
A A
NAND
B B
Z NAND Z
C C
NAND
D D
Z = [ (A • B)' • (C • D)'
= [ (A' + B') ]'
• (C' + D')
= [ (A' + B')' + (C' + D')' ]
]'
= (A • B) + (C • D)
Multi-level Logic
● x = (A + B + C) (D + E) F + G
● Factored form – not written as two-level S-o-P
● 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate
● 10 wires (7 literals plus 3 internal wires)
A
C
B X
D
E
F
G
Conversion of Multi-level Logic to NAND Gates
F = A (B + C D) + B C'
Exclusive-OR Circuits
C
O
u
t
A
B
Label Gate Outputs
A R
B
Out
C S T
A
B
C’
Approach 1: Create Intermediate Equations
B
Out
C S T
A
B
C’
Approach 1: Substitute in subexpressions
A R
B
Out
C S T
A
B
C’
Approach 1: Substitute in subexpressions
C
O
u
t
A
C
’
B
Approach 2: Truth Table
C’
Approach 2: Truth Table
C’
Approach 2: Truth Table
C’
More Difficult Example