BSc Hons.

Physics

HPH207: ELECTRONICS 2

FET AMPLIFIERS

Prof E. Mashonjowa, PhD

 Overview
2

 FET characteristics and modes of

operation
 Analysis and Design of FET

Amplifiers
 bias operating point (DC analysis)
 small signal model (AC analysis)
 Introduction
3

So far we have looked at the bipolar type transistor

amplifier and especially the common emitter
amplifier, but small signal amplifiers can also be
made using Field Effect Transistors (FET’s).
 These devices have the advantage over bipolar

transistors of having an extremely high input

impedance along with a low noise output making
them ideal for use in amplifier circuits that have
very small input signals.
 Introduction
4

 The design of an amplifier circuit based

around a junction field effect transistor  or
“JFET”, (N-channel FET for this course) or
even a metal oxide silicon FET or “MOSFET”
is exactly the same principle as that for the
bipolar transistor circuit used for a Class A
amplifier circuit we looked at before.
 JFET to BJT Comparison
5

Junction FET Bipolar Transistor

Gate, ( G ) Base, ( B )
Drain, ( D ) Collector, ( C )
Source, ( S ) Emitter, ( E )
Gate Supply, ( VG ) Base Supply, ( VB )
Collector Supply,
Drain Supply, ( VDD )
( VCC )
Drain Current, ( ID ) Collector Current, ( IC )
 Field Effect Transistors (FETs)
6

 Advantages of FETs over BJTs:

 Excellent voltage gain
 High input impedance (109-1012 )
 Small physical size, hence occupy very small space in ICs
(widely used in VLSI circuits: >800 million on a single IC
chip)
 Can be used to form circuits with low power consumption
 Good frequency response
 Less noisy as compared to BJT
 Zero temperature drift of output is possible
 Junction Field Effect Transistors (JFETs)
7

n-Channel JFET

p-Channel JFET

The gate, drain, and source correspond roughly to

the base, collector, and emitter of BJTs.
 Device structure of MOSFET (n-type)
8

Gate (G)
Source (S) Oxide Drain (D)
(SiO2)
Metal

n+ Channel area n+

p-type Semiconductor
Substrate (Body)

Body (B)

 For normal operation, it is necessary to create a

conducting channel between Source and Drain
 Creating a channel for current flow
9

 An n channel can be
induced at the top of the
substrate beneath the gate
by applying a positive
voltage to the gate
 The channel is an
inversion layer
 The value of VGS at which a
sufficient number of mobile
electrons accumulate to
form a conducting channel
is called the threshold
voltage (V )
 MOSFET Construction
10

 Two polarities: n-channel and p-channel

 MOSFET Operation
11

 Gate volt controls the thickness of the channel

 Consider an n-channel device
 making the gate more positive attracts electrons to the gate
and makes the gate region thicker – reducing the
resistance of the channel. The channel is said to be
enhanced
 making the gate more negative repels electrons from the
gate and makes the gate region thinner – increasing the
resistance of the channel. The channel is said to be
depleted
 MOSFET Operation
12

 Gates as described above are termed Depletion-

Enhancement MOSFETs or simply DE MOSFETs
 Some MOSFETs are constructed so that in the absence of
any gate voltage there is no channel
 such devices can be operated in an enhancement mode,
but not in a depletion mode (since there is no channel
to deplete)
 these are called Enhancement MOSFETs
 Both forms of MOSFET are available as either
n-channel or p-channel devices
 The effect of varying the gate voltage
13
 MOSFET circuit symbols
14
 C MOSFET Circuit symbol
15

(a) Circuit symbol for the n-channel MOSFET.

(b) Modified circuit symbol with an arrowhead on the source terminal to
distinguish it from the drain and to indicate device polarity (i.e., n
channel).
(c) Simplified circuit symbol to be used when the source is connected to
the body or when the effect of the body on device operation is
unimportant.
 Drain current under small voltage vDS
16

 An NMOS transistor with vGS > Vt and with a small vDS applied.
- The channel depth is uniform and the device acts as a
resistance.
 The channel conductance is
proportional to effective
voltage, or excess gate
voltage, (vGS – Vt) .
 Drain current is proportional
to (vGS – Vt) and vDS.
 Drain current under small voltage vDS
17
 Operation as vDS is increased
18

 The induced channel acquires a tapered shape.

 Channel resistance increases as vDS is increased.
 Drain current is controlled by the two voltages.

B
 Channel pinched off
19

 When VGD = Vt or VGS - VDS = Vt , the channel is pinched

off
 Inversion layer disappears at the drain point
 Drain current does not disappear!
 Output characteristic curves of
20
NMOS

(a) An n-channel enhancement-

type MOSFET with vGS and
vDS applied and with the
normal directions of current
flow indicated. (b) The iD– vDS characteristics
 Output characteristic curves of NMOS
21

• Three distinct regions

 Cutoff region
 Triode region
 Saturation region
 Cutoff region
22

• Biased voltage
vGS  Vt
• The transistor is turned off.

iD  0
• Operating in cutoff region as a switch.
 Triode region
23

• Biased voltage
v GS  V t
v DS  v GS  V t
• The channel depth changes from uniform to tapered shape.
• Drain current is controlled not only by vDS but also by vGS
W  1 2
iD  k n ' ( v
 GS  V t ) v DS  v DS  Process transconductance
L 2 
parameter
W
 kn ' ( v GS  V t ) v DS
L
• Assuming that the drain-source voltage is sufficiently rDS  vDS
small, the MOS operates as a linear resistance iD vGS VGS
 Saturation region
24

• Biased voltage
v GS  V t
v DS  v GS  V t
• The channel is pinched off.
• Drain current is controlled only by vGS
W
iD  1
2 k n ' （ v GS  V t ) 2
L
• Drain current is independent of vDS and behaves as an
ideal current source.
 Drain current under pinch off
25

 Drain current is saturated and only controlled by the vGS

 Drain current controlled by vGS
26

 vGS creates the channel.

 Increasing vGS will increase the conductance of
the channel.
 At saturation region only the v
GS controls the
drain current.
 At sub-threshold region, drain current has an

exponential relationship with vGS

 FET Amplifier Design
27

 Firstly, a suitable quiescent point or “Q-point” needs to be

found for the correct biasing of the JFET amplifier circuit
with single amplifier configurations available for most
FET devices:
 Common-source (CS),
 Common-drain (CD) or Source-follower (SF) and
 Common-gate (CG).
 These three JFET amplifier configurations correspond to
the common-emitter, common collector (emitter-follower)
and the common-base configurations using bipolar
transistors.
Amplifier Topologies
28

Common Source Common Gate Common drain

(Source Follower)
Comparison of Amplifier Topologies
29

Common Source Common Gate Source Follower

 Large Av < 0  Large Av > 0  0 < Av ≤ 1
 Large Rin  Small Rin  Large Rin
– determined by biasing - decreased by RS – determined by biasing

 Rout  RD  Rout  RD  Small Rout

- decreased by RS

 ro decreases Av & Rout  ro decreases Av &  ro decreases Av &

Rout Rout
 FET Amplifiers
30

 In this course we will look at the popular Common

Source JFET Amplifier as this is the most widely
used JFET amplifier design.
 Just as we did with the BJT, we can consider the

FET amplifier analysis in two parts:

 Find the DC operating point
 Then determine the amplifier output parameters for very
small input signals.
 FET Amplifier Design
31

• A FET amplifier circuit should be designed to:

1. ensure that the FET operates in the
saturation region,
2. allow the desired level of DC current
to flow, and
3. couple to a small-signal input source
and to an output “load”.

 Proper “DC biasing” is required!

(DC analysis using large-signal FET model)
 Biasing the JFET
32

n-Channel JFET and Biasing Circuit.

 Operation of JFET at various gate bias
potentials
33

The non-conductive depletion region becomes broader with

increased reverse bias.
 Transfer Characteristics
34

• The input-output transfer characteristic of the JFET is not as

straight forward as it is for the BJT
• In a BJT,  (hFE) defined the relationship between IB (input
current) and IC (output current).
• In a JFET, the relationship (Shockley’s Equation) between
VGS (input voltage) and ID (output current) is used to define
the transfer characteristics: 2
 VGS 
ID = IDSS  1 - 
 VP 

• As a result, FET’s are often referred to a square law devices

 JFET Operating Characteristics
35

There are three basic operating conditions for a JFET:

JFET’s operate in the depletion mode only
A. VGS = 0, VDS is a minimum value depending on IDSS
and the drain and source resistance
B. VGS < 0, VDS at some positive value
C. Device is operating as a Voltage-Controlled Resistor

For an n channel JFET, VGS may never be positive

For an p channel JFET, VGS may never be negative
n-Channel JFET Characteristics and Breakdown

36

Break Down Region

If vDG exceeds the breakdown voltage VB, drain current

increases rapidly.
 Transfer (Mutual) Characteristics of n-Channel JFET
37

2 IDSS
 V 
I I  1  GS 
DS DSS  V 
 P 

VGS (off)=VP
 JFET Transfer Curve
38

• From this graph it is easy to determine the value of I D for a given value of VGS
• It is also possible to determine IDSS and VP by looking at the knee where V GS is 0
 FET output characteristics
39

triode region
 Transfer characteristics
40

 Similar shape for all forms of FET – but with a different

offset
 Not a linear response, but over a small region might be
considered to approximate a linear response
 Normal operating ranges for FETs

41

• However, unlike a bipolar transistor circuit, the FET takes

virtually no input gate current allowing the gate to be treated as
an open circuit.  no input characteristics curves are required.
 Basic MOSFET Amplifier
42

 For large small-signal gain, the MOSFET should be

operated in the saturation region.
 Simple Biasing
43

R
V
GS 2
VDD
R1R 2

 In (a), VGS=VDD, whereas in (b) VGS equals to a

fraction of VDD.
 Simple Bias Circuit: Load Line
44

VDD
RD

VDD
 Self-Biased MOSFET Stage
45

VDD  I D RD  VGS  RS I D

VDD  I D RD  RS   VGS

 Note that there is no voltage

dropped across RG
 M1 is operating in the
saturation region.
 Self Biased Circuit: Load Line
46

VDD
RD  RS

VDD
 Voltage divider bias
47
 Voltage divider bias
48

The amplifier circuit consists of an N-

channel JFET, but could also be an
equivalent N-channel depletion-mode
MOSFET

• The JFET gate voltage Vg is biased through the potential

divider network set up by resistors R1 and R2 and is biased to
operate within its saturation region which is equivalent to the
active region of the bipolar junction transistor.
 Voltage divider biased circuit: Load line
49

 In order to keep the

gate-source junction
reverse biased, the
source voltage, Vs
needs to be higher
than the gate voltage,
Vg.
 FET Amplifier Design
50

 Key amplifier parameters:

(AC analysis using small-signal FET model)
 Voltage gain Av  vout/vin
 Input resistance Rin  resistance seen between the
input node and ground (with output terminal floating)
 Output resistance Rout  resistance seen between the
output node and ground (with input terminal
grounded)