Real Time Implementation of ECG system on FPGA

Objective:
• The ECG signal of the person has to be measured using ECG sensor and analyse using
ordinal pattern analysis , If the threshold value is maximum, status of the patient is
abnormal condition.

• Real-time Electrocardiogram (ECG) monitoring system has to be implemented on Field

Programmable Gate Arrays (FPGA).

• The FPGA chip is taken as the central microprocessor and applies structured design on
Hardware Description Language(HDL) to collect and transmit real-time ECG signals.

• During abnormal condition the buzzer sound will be produced and message is sent to PC
using UART interface.
Block Diagram:

Amplifier & A/D

ECG Sensor
Filter Converter

ECG Data Analysis

Algorithm
FPGA LCD

Clock Frequency 50MHz Spartan 3E

Buzzer
RS232 Cable
ECG Data Analysis Algorithm:

CECG SIGNAL from ECG Sensor

Convert the ECG Signal into .mat or

.txt file

Calculate the ordinal Pattern of

ECG time series

Calculate complexity i.e.,

conditional entropy

Fix the Threshold

THRESHOLD- MAXIMUM– patient

in abnormal condition
Ordinal Pattern Calculation
• Ordinal patterns describe the relations within short segments of length W of a given time series.
• Example: Consider a time series [2.2, 4.5, 3.8, 1.1, 2.5, 6.0 ] of length 6. If the order is 3
Then the ordinal patterns are
Conditional Entropy:
• Entropy detects the dynamic changes and estimates the predictability of time
series.
• The entropy H(X) of a discrete random variable X is defined as
H(X)= -∑ p(x)log(p(x))
• The conditional entropy of ordinal patterns describes the average diversity of the
ordinal patterns succeeding a given ordinal pattern.
• The conditional Entropy is defined as
Conditional entropy= H(PX(d)2) − H(PX(d)).
Where as
PX(d)2 =probability(c(j))
PX(d)= probability(c1(j)=mean(c(j:j+1))
j=1:ly-(m-1)
Threshold for Different Disease:
• Normal person ECG data threshold is 0.0236 and 0.083.
• Abnormal person ECG Data Threshold is

• Minimum Threshold for Abnormal person ECG Data is 0.303

• If the Threshold of the ECG signal is more than 0.3 the suffering from anomaly.
FPGA:
• A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by the customer or designer after manufacturing, hence "field-programmable".
• Selected FPGA is Spartan 3E Starter Kit board
• Internal Embedded Development:
MicroBlaze™ 32-bit embedded RISC processor
PicoBlaze™ 8-bit embedded controller
DDR memory interfaces
Clock Frequency: 50MHz
• 2-line, 16-character LCD screen.
• Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-
amplifier
• Two 9-pin RS-232 ports (DTE- and DCE-style) and Eight discrete LEDs.
• 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface.
• 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash).
ECG Sensor:

• ECG Sensors measure the Bio-potential generated by electrical signals that

control the expansion and contraction of heart chambers.

• Silver-Silver Chloride (Ag‐AgCl) is used as sensor electrode material.

• Interference flexible UART Baud Rate is 57600

• Power consumption is low(<3mW).

Amplifier:
• ECG signals vary from the microvolt to the millivolt range. Due to this small
range, the signals measured need to be amplified in order to be better interpreted.
• Typically bio potential amplifiers have high input impedance and are designed for
safety.
• The output impedance of the amplifier should be very low to drive any external
load with minimal distortion. Again, due to the small size of the signal, the gain
should be large.
Input Impedance: High(1MOhm)
Gain: More than 1000
High CMRR(Common mode rejection ratio)
Future work:
• The ECG sensor has to be connected to operational amplifier and filter.

• ADC,LCD and UART (RS 232) have to be interfaced to the FPGA board(Spartan
3E).

• Person Abnormal condition to be sent to LCD and PC through UART interface.

Thank You