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    128K X 8 High Speed Full CMOS 6T - 4

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    anwar sayeed
    This document summarizes the design of a 128K x 8 high speed full CMOS 6T SRAM using 65nm technology. Key aspects include a timing circuit that is 15% complete, specifications for high speed operation at 10ns with low active and standby power, and a block diagram showing the divide word line architecture. Monte Carlo simulations show the cell achieving 100% yield for read, write, and static noise margins with tight distributions. Layouts are presented for the memory array, write driver, sense amplifier, and address transition detection circuit.

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    128K X 8 High Speed Full CMOS 6T - 4

    Uploaded by

    anwar sayeed
    18 views32 pages
    This document summarizes the design of a 128K x 8 high speed full CMOS 6T SRAM using 65nm technology. Key aspects include a timing circuit that is 15% complete, specifications for high speed operation at 10ns with low active and standby power, and a block diagram showing the divide word line architecture. Monte Carlo simulations show the cell achieving 100% yield for read, write, and static noise margins with tight distributions. Layouts are presented for the memory array, write driver, sense amplifier, and address transition detection circuit.

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    128K x 8 High Speed Full CMOS 6T_4

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    This document summarizes the design of a 128K x 8 high speed full CMOS 6T SRAM using 65nm technology. Key aspects include a timing circuit that is 15% complete, specifications for high speed operation at 10ns with low active and standby power, and a block diagram showing the divide word line architecture. Monte Carlo simulations show the cell achieving 100% yield for read, write, and static noise margins with tight distributions. Layouts are presented for the memory array, write driver, sense amplifier, and address transition detection circuit.

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    © All Rights Reserved
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    18 views32 pages

    128K X 8 High Speed Full CMOS 6T - 4

    Uploaded by

    anwar sayeed
    This document summarizes the design of a 128K x 8 high speed full CMOS 6T SRAM using 65nm technology. Key aspects include a timing circuit that is 15% complete, specifications for high speed operation at 10ns with low active and standby power, and a block diagram showing the divide word line architecture. Monte Carlo simulations show the cell achieving 100% yield for read, write, and static noise margins with tight distributions. Layouts are presented for the memory array, write driver, sense amplifier, and address transition detection circuit.

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    © All Rights Reserved
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    of 32

    128K x 8 High Speed

    Full CMOS 6T SRAM


    using 65nm Technology
    PRESENTED BY :
    MANU KASHYAP(2018CRF2531), MANISH KUMAR SINGH(2018CRF2528), RAKESH GUPTA(2018VST9025)

    UNDER THE GUIDANCE OF


    DR. KAUSHIK SAHA
    15% Work Remaining
    Timing Circuit in Progress
    & Top Level Integration is due
    Specifications: Reference :
    1. VCC = 1.2 V CY7C1019CV33
    2. High Speed: tAA = 10ns
    3. Low Active Power: ICC = 60 mA @ 10 ns
    4. Low CMOS Standby Power: ISB = 3 mA
    5. 0.7 V Data retention

    Additional Features:
    1. Automatic power-down when deselected
    2. Easy memory expansion with CE and OE options
    Block Diagram:
    Divide Word Line Architecture
    Pin Configuration
    Floor Plan &
    Architecture:

    6T-SRAM
    16KB Block
    Diagram.
    Metal Routing Plan

    ME7: Power Net of Chip


    ME6: Ground Net of Chip
    ME5: GLOBAL ROUTING
    ME4: GLOBAL ROUTING
    ME3: BL/BLN
    ME2: Word Line
    ME1: LOCAL CONNECTIONS
    POLY
    Layout of 16x16 Memory Array
    Corrected Twisted BL/BLN
    1.355 um
    Corrected

    Area Estimation:
    • w/l(PUN) = 100/60; w/l(PDN) = 195/60;
    w/l(Access_Transistor) = 100/80
    1.325 um
    • Area of 1-Bit Cell = 1.355(W) * 1.125(H) =
    1.524 um^2
    • Size of 16 KB Memory Block: 0.321 mm^2

    Total Size of Memory Array = 2.57 mm^2


    Assuming 65% Core Efficiency, Total Chip
    Area = 3.95 mm^2
    Monte Carlo Simulation
    6T Cell Read Noise Margin Plot for 100 Points Mismatch

    RNM= 261.06 mV
    SD = 1.0163 mV
    Yield 100%
    Monte Carlo Simulation
    6T Cell Read Noise Margin Plot for 100 Points
    Process+Mismatch

    RNM= 261.06 mV
    SD = 0.9420 mV
    Yield 100%
    Monte Carlo Simulation
    6T Cell Write Noise Margin Plot for 100 Points Mismatch

    WNM= 571.69 mV
    SD = 1.0051 mV
    Yield 100%
    Monte Carlo Simulation
    6T Cell Write Noise Margin Plot for 100 Points
    Process+Mismatch

    WNM= 571.69 mV
    SD = 0.8736 mV
    Yield 100%
    Monte Carlo Simulation
    6T Cell Static Noise Margin Plot for 100 Points Mismatch

    SNM= 540.91 mV
    SD = 1.1624 mV
    Yield 100%
    Monte Carlo Simulation
    6T Cell Static Noise Margin Plot for 100 Points
    Process+Mismatch

    SNM= 540.91 mV
    SD = 0.9603 mV
    Yield 100%
    Writer Driver Circuit
    Delay = 67.85 pS Write Driver Schematic

    Driver Part Control Part


    Write Driver Layout
    Worst Case
    Delay = 113.68 pS

    Delay PVT Analysis of Write Driver


    Process Corner -40º C 27º C 85º C

    FF 39.95 pS 40.67 pS 41.27 pS


    FnSp 59.76 pS 60.59 pS 61.52 pS
    TT 66.88 pS 67.85 pS 70.85 pS
    SnFp 75.23 pS 77.46 pS 81.66 pS
    SS 106.49 pS 109.72 pS 113.68 pS
    Proposed Sense Amplifier
    Delay as Per
    This
    Architecture =
    43.4 pS
    Sense Amplifier BL/BLN
    Calculated
    Differential Voltage
    Delay = 48.8 pS
    = 60 mV
    Sense Amplifier Layout
    Monte Carlo Simulation
    Sense Amplifier Histogram Plot for 100 Points Process
    Variation

    Yield = 100 %
    ( 99.7 % within 6 sigma)
    Address Transition Detection Circuit

    XOR
    using
    DPL
    Logic
    Pulse Width = Output Waveform of ATD
    823.3 pS ( Calculating All the Delay)
    Monte Carlo Simulation
    ATD Delay Histogram Plot for 100 Points
    Process+Mismatch
    Yield = 100 %
    ( 99.7 % within 6 sigma)
    Timing & Control Circuit Simulation
    Read Critical Path Simulation
    Write Critical Path Simulation
    Thanks

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