Computer Architecture

Lecture – 9
 A Branch instruction replaces the contents of
PC with the Branch Target Address.
 This address is determined by adding an offset
value, X, to the updated value of the PC which
is given in the branch instruction.
 Following is an example of implementing
unconditional Branch Instruction.
 The first 3 steps which constitutes the Fetch
Phase is same for all instructions.
 So, the first 3 steps are same as the previous :
1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin ,WMFC
3. MDRout, IRin
 The fetch phase ends when the fetched
instruction is loaded into IR.
 Then the branch instruction is taken to decoding
circuit, where the offset value is extracted from
the instruction.
 While finding out the offset, the decoding
circuit also performs sing extension, if
necessary.
 Step 4 :
4. Offset-field-of-IRout, Add, Zin
▪ In step 4, the updated value of PC is already available in
the register Y.
▪ The offset, X is gated on to the bus from decoding
circuit.
▪ The offset value is added with the updated value of PC
and temporarily stored in Z.
 Step 5 :
 Zout, PCin, End.
▪ In final step, the branch target address, which is found
from the addition is taken from Z and loaded into PC.
 How Offset address is calculated :
 Normally, the difference between target address
and the address of the instruction which
immediately follows the branch instruction is said
as the Offset value.
 Let, the instructions are byte addressable and each
instruction consists of 4 bytes.
 Assume, the branch instruction is at address 2000.
 And, the target address is 2050.
 During the fetch phase of the Branch instruction
located at 2000, the PC is updated with the
address of the instruction that follows the branch
instruction, which is 2004
 So, the offset value is : 2050 – 2004 = 46.
 Now consider an conditional Branch
instruction.
 Here, we have to check the status of the
condition codes before loading the new value
into the PC.
 And, here, the condition is if the status is
negative then branching is performed,
otherwise consecutive instructions are
performed.
 So, we call it Branch-on-negative instruction.
 We denote, the status as N.
 So, N = 1 means condition is true, then
branching happens and the PC is loaded with
the new value.
 And when N = 0 means condition is false, and
the program ends, that is, returns to step 1.
 For this instruction, also the Fetch phase is
same.
 So the Fetch phase :
1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin ,WMFC
3. MDRout, IRin
 The Execution Phase :
4. Offset-field-of-IRout, Add, Zin, if N = 0 then End
5. Zout, PCin, End
 This if N = 0, the processor returns to step 1
immediately after step 4.
 If N = 1, step 5 is performed to a new value
into the PC, the performing the branch
operation.
 In the beginning we have learned an
organization of processor which consists of
only one inter processor bus.
 But a problem is with this single bus
organization, for performing one instruction
lots of control step is needed, that is the
control sequence becomes long.
 The reason for this, there is only one path for
the transfer of the data.
 To reduce the number of steps, processors can
have multiple internal buses in different way.
 This provides several paths for data transfer,
so multiple transfer takes place in parallel.
 Here, we will explain a three-bus organization
processor's structure use to connect the
registers and the ALU.
 But other different organization is also
possible.
 Important components of three-bus(A, B & C)
structure of the processor :
 Register File
▪ All general purpose registers are combined into a single
block, called Register File.
▪ The number of register is implemented in the form of an
array of memory cells.
▪ Here, the register file has three ports.
▪ There are two outputs, so that the contents of two
different registers can be accessed simultaneously.
 ▪ Because of having the two outputs, the content of two
registers can be placed on the buses A and B.
▪ The third port is used to load the data of Bus C into
another register during the same clock cycle.
▪ So, data transfer from or to three registers can be
performed simultaneously.
 ALU
▪ Bus A and B provides the two operands to two inputs A
and B of the ALU.
▪ Of this, the contents of Bus A passes through a
Multiplexer.
Bus A Bus B Incrementer Bus C

PC

Register Three Bus Organization

File of the DataPath
Constant 4
M AA
U LR
X U
B
Instruction Decoder

IR

MDR

MAR

Memory Bus Address Line

Data Lines
▪ Like the single bus organization, either the contents of
Bus A is selected otherwise constant value 4 is selected.
▪ The ALU performs the desired operation on the two
operands and passes the result on the Bus C
directly(without any modification).
▪ To have the data at any input of ALU as the result, two
control signals are used, that is, R = A and R= B.
▪ So, here the register Y and Z of the single bus
organization are not needed.
 Incrementer Unit :
▪ This unit is used to increment the PC by 4.
▪ Using this unit eliminates the need of adding 4 to the PC
using main ALU for every instruction.
▪ But still, here a provision is kept to add 4 to the other input
of the ALU.
▪ This is used for other purposes, that is, to increment
other addresses.
▪ For example, the memory addresses in LoadMultiple and
StoreMultiple instruction where multiple instructions are
to be fetched at the same time.
 Example :
 Add R4,R5,R6
 That is, add the contents of R4 & R5 and store the sum
in R6.
 Control sequences :
1. PCout, R = B, MARin, Read, IncPC
▪ The content of PC is passed through ALU to Bus C.
▪ This is done because MAR register takes input from Bus C, so
value of PC is loaded into MAR.
▪ This starts the memory Read operation and also at the same
time the PC in incremented by 4.
2. WMFC
▪ The memory Read operation that started in step 1, in
step 2 , processor waits for that function to be
completed, that is waits for MFC signal.
3. MDRoutB, R = B, IRin
▪ In this step, memory Read operation is completed.
▪ From MDR, the instruction is sent to Bus B.
▪ From Bus B the instruction is sent to Bus C via ALU.
▪ This is done to load that instruction into IR(IR takes its
input from Bus C)
 These 3 steps constitutes the Fetch Phase.
 After that only one step is needed in Execution
Phase :
4. R4outA, R5outB, SelectA, Add, R6in, End
▪ Content of R4 is taken into Bus A and R5 into Bus B
▪ In the select input of MUX is instructed to select the
content of Bus A as input of ALU(A)
▪ Then addition is performed in the ALU and the result is
loaded into R6 via Bus C.
▪ After that, the execution ends.
 Zaky
 Chapter 7 : 7.2(7.2.1), 7.3
 Class Lecture

09/23/22 Sumaiya Iqbal, Lecturer, CSE, BUET