DATA TYPES IN SYSTEM

VERILOG

.
 Content
 Definition
 Integer data types
 Real and shortreal data types
 Void data type
 String data type
 Event data type
 User-defined types
 Enumerations
 Structures and unions
 Class
 Singular and aggregate types
 chandle data type
 Casting
 Definition

A data type simply is a classification of

data which tells the compiler how the
programmer intends to use the data.
 Integer data types
 SystemVerilog offers several integer data types

 shortint 2-state SV data type, 16 bit signed integer

int 2-state SV data type, 32 bit signed integer
longint 2-state SV data type, 64 bit signed integer
byte 2-state SV data type, 8 bit signed integer or
ASCII character
bit 2-state SV data type, user-defined vector size
logic 4-state SV data type, user-defined vector size
reg 4-state Verilog-2001 data type, user-defined
vector size
integer 4-state Verilog-2001 data type, 32 bit signed integer
time 4-state Verilog-2001 data type, 64-bit unsigned integer
 Integer data types
SV offers several integer data types. representing a hybrid of both Verilog and C data
types

data types state Size(bits) Default value

shortint 2 16 signed
int 2 32 signed
longint 2 64 signed
byte 2 8 signed
bit 2 user-defined vector Unsigned
logic 4 user-defined vector Unsigned
reg 4 user-defined vector Unsigned
integer 4 32 signed
time 4 64 unsigned
4 State and 2 State Data Types
 Values are supported in 4-state types(0,1,x,z ).
 These are- logic, reg, integer and time.

 where as 2 state data types have only 0 and 1.

 These are bit, byte, shortint, int, longint.

 2-state data types can simulate faster, take less memory.

Signed and unsigned data types

The data types byte, shortint, int, longint and integer default to signed.
The data types bit, reg ,time and logic default to unsigned as do arrays of
these types.

This affects the meaning of certain operators such as relational

operator(<,>,<=,>= ).

Syntax - data_type signed/unsigned variable_name;

The real data type is same as a C double. (8 byte)

The shortreal data type is same as a C float.(4 byte)
 Logic
 Functionality same as reg.

 But used anywhere that the reg and net data types are
traditionally used (same as verilog) except inout and
multiple drives.

 Used for both combination and sequential design .

(helps in removing the confusion in verilog )
module data_types(); $display("data_1bit = %0d",data_1bit);
bit data_1bit; $display("data_8bit = %0d",data_8bit);
byte data_8bit; $display("data_16bit = %0d",data_16bit);
shortint data_16bit; $display("data_32bit = %0d",data_32bit);
int data_32bit; $display("data_64bit = %0d",data_64bit);
longint data_64bit; $display("data_integer = %0d",data_integer);
integer data_integer; data_1bit = {32{4'bzx01}};
data_8bit = {32{4'bzx01}};
data_16bit = {32{4'bzx01}};
bit unsigned data_1bit_unsigned;
data_32bit = {32{4'bzx01}};
byte unsigned data_8bit_unsigned;
data_64bit = {32{4'bzx01}};
shortint unsigned data_16bit_unsigned;
data_integer= {32{4'bzx01}};
int unsigned data_32bit_unsigned;
$display("data_1bit = %b",data_1bit);
longint unsigned data_64bit_unsigned;
$display("data_8bit = %b",data_8bit);
integer unsigned data_integer_unsigned;
$display("data_16bit = %b",data_16bit);
$display("data_32bit = %b",data_32bit);
initial begin $display("data_64bit = %b",data_64bit);
data_1bit = {32{4'b1111}}; $display("data_integer = %b", data_integer);
data_8bit = {32{4'b1111}}; data_1bit_unsigned = {32{4'b1111}};
data_16bit = {32{4'b1111}}; data_8bit_unsigned = {32{4'b1111}};
data_32bit = {32{4'b1111}}; data_16bit_unsigned = {32{4'b1111}};
data_64bit = {32{4'b1111}}; data_32bit_unsigned = {32{4'b1111}};
data_integer= {32{4'b1111}}; data_64bit_unsigned = {32{4'b1111}};
data_integer_unsigned = {32{4'b1111}};
$display("data_1bit_unsigned =
%d",data_1bit_unsigned);
$display("data_8bit_unsigned =
%d",data_8bit_unsigned);
$display("data_16bit_unsigned =
%d",data_16bit_unsigned);
$display("data_32bit_unsigned =
%d",data_32bit_unsigned);
$display("data_64bit_unsigned =
%d",data_64bit_unsigned);
$display("data_integer_unsigned =
%d",data_integer_unsigned);
data_1bit_unsigned = {32{4'bzx01}};
data_8bit_unsigned = {32{4'bzx01}};
data_16bit_unsigned = {32{4'bzx01}};
data_32bit_unsigned = {32{4'bzx01}};
data_64bit_unsigned = {32{4'bzx01}};
data_integer_unsigned = {32{4'bzx01}};
$display("data_1bit_unsigned =
%b",data_1bit_unsigned);
$display("data_8bit_unsigned =
%b",data_8bit_unsigned);
$display("data_16bit_unsigned =
%b",data_16bit_unsigned);
$display("data_32bit_unsigned =
ompiler version J-2014.12-SP1-1; Runtime version J-2014.12-SP1-1; Mar
22 10:17 2017
data_1bit = 1
data_8bit = -1
data_16bit = -1
data_32bit = -1
data_64bit = -1
data_integer = -1
data_1bit = 1
data_8bit = 00010001
data_16bit = 0001000100010001
data_32bit = 00010001000100010001000100010001
data_64bit =
000100010001000100010001000100010001000100010001000100010001
0001
data_integer = zx01zx01zx01zx01zx01zx01zx01zx01
data_1bit_unsigned = 1
data_8bit_unsigned = 255
data_16bit_unsigned = 65535
data_32bit_unsigned = 4294967295
data_64bit_unsigned = 18446744073709551615
data_integer_unsigned = 4294967295
data_1bit_unsigned = 1
data_8bit_unsigned = 00010001
data_16bit_unsigned = 0001000100010001
data_32bit_unsigned = 00010001000100010001000100010001
data_64bit_unsigned =
000100010001000100010001000100010001000100010001000100010001
0001
data_integer_unsigned = zx01zx01zx01zx01zx01zx01zx01zx01
$finish called from file "testbench.sv", line 68.
$finish at simulation time 1
VCS Simulation Report
Real and shortreal data types

The real data type is a Verilog-2001, and is the same as

a C double(64 bit).
The shortreal data type is a SystemVerilog data type,
and is the same as a C float(32 bit).
It is a 2 state variable by default unsigned.

 Ex-real data_real;
data_real = {32{4'b1111}};
$display(" data_real = %0f", data_real);
data_real = {32{4'bzx01}};
$display(" data_real = %f", data_real);

O/P- data_integer = 340282366920938463463374607431768211456.000000

data_integer = 22685491128062563916067208304141533184.000000
 Void data type

The void data type represents non-existent

data.

This type can be specified as the return type

of functions, indicating no return value.
 String
 string data type, which is a variable size, dynamically allocated
array of bytes.
 string data type is used for storing strings
 Variables of type string can be indexed from 0 to N-1.
 They can take on the special value “ ”
 Syntax – string variable_name [= initial_value];
 String Operators
o Str1 = = Str2, Str1 != Str2, <, >, <=, =>,
{Str1,Str2,...,Strn},{multiplier{Str}} , Str.method(...),
Str[index]
module string_ex ();
string str1 = "tessolve";
string str2;
byte a="A"; // byte a="AB"; output-a=B
bit [0:1][0:7]b=" AB"; //output=AB
bit [0:4][0:7]b=" AB"; //output= AB
bit [0:8][0:7]b=" AB"; //output= AB
initial
begin
$display("str1=%s",str1);
output-str1=tessolve
$display("str1=%h",str1);
$display("str2=%s",str2); str1=746573736f6c7665
$display("str2=%h",str2); str2=
$display("a=%s",a); str2=00
end a=A
endmodule
String
 String build in Tasks
o len() -Returns length of string.
o putc() -Used to assign one character of string.
o getc() -Returns a character.
o toupper() -Returns the uppercase of string.
o tolower() -Returns the lowercase of string.
o compare() -Returns the string compare result .
o icompare()-Returns caseless string compare result
o substr() -Returns the sub string of main string.
module string_ex ();
string str1 = "tessolve";
string str2,str;
initial
begin Output-
$display("str1=%h",str1); Compiler version J-2014.12-
$display("length of str2=%d“ , SP1-1; Runtime version J-
str2.len() ); 2014.12-SP1-1; Mar 14
$display("str1[5]=%s",str1[5]);
11:35 2017
str2=str1.toupper();
$display("str2=%s",str2);
str1=746573736f6c7665
$display("str2=%h",str2); length of str2= 0
if (str2.tolower!=str1) str1[5]=l
$display("both r not same"); str2=TESSOLVE
else str2=544553534f4c5645
$display("both r same"); both r same
$display("length of str2=%d",str2.len());
length of str2= 8
str1.putc(3,"Sorry");
$display("str1=%s",str1);
$display("str1=%s",str1.getc(3));
$display("%d",str1.compare(str2));
str1=tesSolve
if(str1.compare(str2)) //non zero
str1=S
$display("both r same");
32
else
both r same
$display("both r not same");
0
$display("%d",str1.icompare(str2));
both r not same
if(str1.icompare(str2)) //zero
str=sSol
$display("both r same");
VCS Simulation R
else
eport
$display("both r not same");
str= str1.substr(2,5);
$display("str=%s",str);
end
endmodule
String build in Tasks

o atoi()
o atohex()
o atooct()
o atobin()
o atoreal()
o itoa()
o hextoa()
o octtoa()
o bintoa()
o realtoa()
module string_ex ();
string str1 = “tessolve";
string str2,str; Output-
string str3 = "102.11tess454546olve";
integer value of str1= 0
Initial
integer value of str3= 102
begin
$display("integer value of str1=%d", hexadecimal value of str3=
str1.atoi()); 258
$display("integer value of str3=%d", octal value of str3= 66
str3.atoi()); binary value of str3=
$display(“hexadecimal value of str3= 000000000000000000000000000
%d", str3.atohex()); 00010
$display(“octal value of str3=%d",
str3.atooct());
$display(“binary value of str3=%b",
str3.atobin());
$display(“real value of str3=%g",
str3.atoreal());
str1.itoa(653266);
$display("str1=%s",str1);
str1.hextoa(653266);
$display("str1=%s",str1); real value of str3=102.11
str1.octtoa(653266);
str1=653266
$display("str1=%s",str1);
str1=9f7d2
str1.bintoa(653266);
str1=2373722
$display("str1=%s",str1);
str1=1001111101111101001
str1.realtoa(653266.12);
0
$display("str1=%s",str1);
str1=653266
end
VCS Simulation
endmodule
Report
 Event data type
 Events provide a handle to a synchronization object.

 Syntax:
event variable_name [= initial_value];

 An identifier declared as an event data type is called a named event and

has no storage.

 A named event can be triggered explicitly using "->" .

and recognized by using the event control "@" .
 Event data type Ex
module main; initial
event e; #100 $finish;
Initial endmodule
Output-
repeat(1)
Compiler version J-2014.12-SP1-1; Runtime
begin version J-2014.12-SP1-1; Mar 14 12:43 2017
#20; ->e ; e is FALSE at 10
$display(" e is triggered at %t ",$time); e is triggered at 20
end e is TRUE at 20
always e is FALSE at 30
e is FALSE at 40
begin
e is FALSE at 50
#10;
e is FALSE at 60
if(e.triggered) e is FALSE at 70
$display(" e is TRUE at %t",$time); e is FALSE at 80
else e is FALSE at 90
$display(" e is FALSE at %t",$time); $finish called from file "testbench.sv", line 16.
end $finish at simulation time 100
VCS Simulation Repor
 Event data type

The "triggered“ event property evaluates to true if the

given event has been triggered in the current time-step and
false otherwise

In SystemVerilog , Named Event triggering occurrence can

also be recognized by using the event control wait().

Wait() statement gets blocked until it evaluates to TRUE.

 Compiler version J-2014.12-SP1-1; Runtime version J-2014.12-
SP1-1; Mar 14 13:01 2017
module event_m;
ONE :: EVENT A is triggered at time 20
event a; TWO :: EVENT A is triggered at time 20
initial ONE :: EVENT A is triggered at time 40
repeat(5) ONE :: EVENT A is triggered at time 60
TWO :: EVENT A is triggered at time 60
#20 -> a;
ONE :: EVENT A is triggered at time 80
always ONE :: EVENT A is triggered at time 100
begin TWO :: EVENT A is triggered at time 100
@a; VCS Simulation Report
$display(" ONE :: EVENT A is triggered at time %t",$time);
end
always
begin
wait(a.triggered);
$display(" TWO :: EVENT A is triggered at time %t",$time);
#30;
end
endmodule
 Operators on event-

Equality (= =) with another event or with null.

Inequality (!=) with another event or with null.
 Case equality (= = =) with another event or with null
Case inequality (!= =) with another event or with null

 Test for a Boolean value that shall be 0 if the event is null

and 1 otherwise.
module main;
if(e3 == e2)
event e1,e2,e3,e4;
$display( " e3 and e2 are same events ");
initial
else
begin
$display( " e3 and e2 are not same events");
e1 = null;
end
e2 = e3;
endmodule
if(e1)
Output-
$display(" e1 is not null ");
e1 is null
else
e2 is not null
$display(" e1 is null ");
e3 and e4 are not same events
if(e2)
e3 and e2 are same events
$display(" e2 is not null");
VCS Simulation Report
else
$display(" e2 is null");
if(e3 = = e4)
$display( " e3 and e4 are same events ");
else
$display( " e3 and e4 are not same events");
User defined types
Using this, a user can define his own data types.
Syntax:
o typedef data_type type_identifier variable_dimension ;
o typedef [ enum | struct | union | class ] type_identifier;

Example:
o typedef integer myinteger;
o typedef bit[3:0] nibble ;
o typedef struct { byte a; reg b; shortint unsigned c; } myStruct;
o typedef enum { red, green, blue, yellow, white, black } Colors ;
 A type can be used before it is
module main; defined, provided it is first
identified as a type by an empty
typedef int my; typedef:
initial module main;
begin typedef my;
my a=5; my f = 5;
$display ("a=%d", a); typedef int my;
end initial
endmodule begin
$display ("f=%d", f);
Runtime version J-2014.12-SP1-1;
end
Mar 14 13:22 2017
endmodule
a= 5
Runtime version J-2014.12-SP1-1;
VCS Simulation Repo Mar 14 13:25 2017
rt f= 5
VCS Simulation Report
 Enumeration datatype

 An enumeration is a user-defined data type that consists of integral named constants.

 It provide the capability to abstractly declare strongly typed variables without either a
data type and later add the required data type and values as per designs requirement.

 It is a special way of creating your own Type

 The default data type shall be int.

 Syntax
enum [ enum_base_type ] { enum_name_declaration { , enum_name_declaration } }
Example
o enum integer {IDLE=0, GNT0=1, GNT1=2} state;
o enum {RED,GREEN,ORANGE} color;
o enum {BRONZE=4, SILVER, GOLD} medal;
o enum {a, b=7, c} alphabet;
Error
 cases

oassignment with x or z assigned to an enum with no explicit data type or an explicit 2-

state declaration .
enum {IDLE, XX=’x, S1=2’b01, S2=2’b10} state, next;
// Syntax error: IDLE=2’b00, XX=2’bx <ERROR>, S1=2’b01, S2=2’b10
ounassigned enumerated name that follows an enum name with x or z assignments
enum integer {IDLE, XX=’x, S1, S2} state, next;
// Syntax error: IDLE=2’b00, XX=2’bx, S1=??, S2=??
oIf an automatically incremented value is assigned elsewhere in the same enumeration
enum {a=0, b=7, c, d=8} alphabet;
// Syntax error: c and d are both assigned 8

oAny enumeration encoding value that is outside the representable range of the enum.
enum bit [3:0] {bronze=5'h13, silver, gold=3'h5} medal4;
// Error in the bronze and gold member declarations
SystemVerilog includes a set of specialized methods to enable iterating over
the values of enumerated types.

o first()
o last()
o next()
o prev()
o num()
o name()
module xx;
typedef enum {Red,Green,
Blue,yellow,white,crown} colors;
colors c,c1;
initial
begin
Compiler version J-2014.12-SP1-
$display ("first element is %d",c.first);
1; Runtime version J-2014.12-
c1=c.first;
SP1-1; Mar 22 06:07 2017
$display ("first element is %s",c1.name);
first element is 0
c1=c1.next;
first element is Red
$display ("next element is %s",c1.name);
c1=c1.prev;
next element is Green
$display ("prev element is %s",c1.name);prev element is Red
$display ("last element is %d",c.last); last element is 5
$display ("no of element is %d",c.num);no of element is 6
end VCS Simulation Repor
endmodule t
module enum_ex;
Compiler version J-2014.12-SP1-1; Runtime
typedef enum { red, green=3, blue[8], version J-2014.12-SP1-1; Mar 15 05:45 2017
yellow[1:5]=14 } Colors; name=red :value= 0
name=green :value= 3
initial name=blue0 :value= 4
begin name=blue1 :value= 5
name=blue2 :value= 6
Colors c = c.first;
name=blue3 :value= 7
forever name=blue4 :value= 8
begin name=blue5 :value= 9
name=blue6 :value= 10
$display( "name=%s :value= %d", c.name, name=blue7 :value= 11
c ); name=yellow1 :value= 14
if( c == c.last ) break; name=yellow2 :value= 15
name=yellow3 :value= 16
c = c.next; name=yellow4 :value= 17
end name=yellow5 :value= 18
the total no of element in enum is 15
$display ("the total no of element in enum
VCS Simulation Report
is %d",c.num );
end
endmodule
 Structure
 structure is an user defined data type that allows to
combine data items of different kinds.
 structure data types to declare complex data type, which is
nothing but a collection of other data types.
 Syntax
struct [structure tag] { member definition;
member definition;
...
member definition; }[one or more structure variables];
 To access any member of a structure, we use the
member access operator (.).
 Structure
module struct_data ();
struct data{ byte a;
reg b;
shortint unsigned c; } myStruct;

myStruct = '{11,1,101};
initial begin
$display ("a = %b b = %b c = %h", myStruct.a, mystruct.b, mystruct.c); // 1011 1 65
#1 $finish; end
endmodule
module mod1;
typedef struct packed {
int x;
int y; } st;
st s1;
int k = 1;
initial begin
#1 s1 = {1, 2+k}; Compiler version J-2014.12-SP1-1;
#1 $display( s1); Runtime version J-2014.12-SP1-1; Mar
20 10:00 2017
#1 $display( s1.x, s1.y);
4294967299
#1 s1 = {x:2, y:3+k}; 13
#1 $display( s1.x, s1.y); 24
#1 $display( s1); 8589934596
#1 $finish; $finish called from file "testbench.sv",
line 14.
end
$finish at simulation time 5
endmodule
VCS Simulation Report
 Class
 A class is a collection of data (class properties)and a
set of subroutines(methods) that operate on that data.

 Class instances, or objects, can be passed around via

object handles.

 The object-oriented class extension allows objects to

be created and destroyed dynamically.
 Singular and aggregate types
 Data types are categorized as either singular or
aggregate.
 A singular type shall be any data type except an unpacked
structure, union, or array .
 A singular variable or expression represents a single
value, symbols, or handle.
 An aggregate type shall be any unpacked structure, union,
or array data type.
 Aggregate expressions and variables represent a set or
collection of singular values.
 \

chandle data type

The chandle data type represents storage for pointers

chandleis a special SystemVerilog type that is used for passing C pointers as arguments to imported DPI
functions.

The size of this type is platform dependent, but shall be at least large enough to hold a pointer on the
machine in which the tool is running
syntax :
chandle variable_name ;

Chandlesshall always be initialized to the value null

Only == ,!= ,=== ,!== operators are valid with another chandle or with null .

restriction:
— Ports shall not have the chandle data type
— Chandles shall not be assigned to variables of any other type
— Chandles shall not be used:
As ports
In sensitivity lists or event expressions.
 Casting
 type casting is used for converting one type of data type to
another type of data type , by using a cast (') operation.

 The expression to be cast must be enclosed in parentheses

or within concatenation or replication braces and is self-
determined.

 Example
int a ;
a = int‘ (2.3 * 3.1); // 7(below X.5 =X)
a = int‘ (2.3 * 3.3); // 8(above and equal X.5 =X+1)
module enum_ex;
typedef enum {Red, Green, Blue} Colors;
typedef enum {Mo,Tu,We,Th,Fr,Sa,Su} Week;
Colors C;
initial
begin
C = Colors'(C+1);
$display ("element=%s value=%d", C.name,C);
output-
C = Colors'(Su);
Compiler version J-2014.12-SP1-1;
$display ("element=%s value=%d", C.name,C);
Runtime version J-2014.12-SP1-1;
// out of range value Mar 15 07:02 2017
C = Colors'(Mo); element=Green value= 1
$display ("element=%s value=%d", element= value= 6
C.name,C);
element=Red value= 0
end
VCS Simulation Repo
endmodule
rt
Dynamic casting
 It is used to assign values to variables that might not ordinarily be
valid.
 Done by system task-$cast
 Syntax:-task cast( singular dest_var, singular source_exp );
function int $cast( singular dest_var, singular source_exp );
 Both cases $cast attempts to assign the source expression to the
destination variable.
 In case of task If the assignment is invalid,
 a runtime error occurs
 the destination variable is left unchanged.
 In case of function
 returns 1 if the cast is legal.and
 If the cast fails, the function does not make the assignment and returns 0.
 $cast performs a run-time check.
 No type checking is done by the compiler, except to check
that the destination variable and source expression are
singulars.
 Ex:-
typedef enum { red, green, blue, yellow, white, black }
Colors;
Colors col;
$cast( col, 2 + 3 ); //col=5(black)

More examples needed

THANK
YOU