William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 3
Top Level View of Computer
Function and Interconnection
Program Concept
• Hardwired systems are inflexible
• General purpose hardware can do
different tasks, given correct control
signals
• Instead of re-wiring, supply a new set of
control signals
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals
• We have a computer!
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• Combination of above
Example of Program Execution
Details

1. The PC contains 300, the address of the first instruction. This instruction
(the value 1940 in hexadecimal) is loaded into the instruction register IR
and the PC is incremented. Note that this process involves the use of a
memory address register (MAR) and a memory buffer register (MBR). For
simplicity, these intermediate registers are ignored.
2. The first 4 bits (first hexadecimal digit) in the IR indicate that the AC is to
be loaded. The remaining 12 bits (three hexadecimal digits) specify the
address (940) from which data are to be loaded.
3. The next instruction (5941) is fetched from location 301 and the PC is
incremented.
4. The old contents of the AC and the contents of location 941 are added and
the result is stored in the AC.
5. The next instruction (2941) is fetched from location 302 and the PC is
incremented.
6. The contents of the AC are stored in location 941.
Instruction Cycle State Diagram
• Instruction fetch (if): Read instruction from its memory
location into the processor.
• Instruction operation decoding (iod): Analyze instruction to
determine type of operation to be performed and
operand(s) to be used.
• Operand address calculation (oac): If the operation
involves reference to an operand in memory or available
via I/O, then determine the address of the operand.
• Operand fetch (of): Fetch the operand from memory or
read it in from I/O.
• Data operation (do): Perform the operation indicated in the
instruction.
• Operand store (os): Write the result into memory or out to
I/O.
Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
• Program
—e.g. overflow, division by zero
• Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking
• I/O
—from I/O controller
• Hardware failure
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts - Sequential
• The drawback to the preceding approach is that
it does not take into account relative priority or
time-critical needs.
• For example, when input arrives from the
communications line, it may need to be absorbed
rapidly to make room for more input. If the first
batch of input has not been processed before the
second batch arrives, data may be lost.
Multiple Interrupts – Nested
Multiple Interrupts – Nested
• A second approach is to define priorities for
interrupts and to allow an interrupt of higher
priority to cause a lower-priority interrupt
handler to be itself interrupted
Multiple Interrupts Example
• Consider a system with three I/O devices: a printer, a disk,
and a communications line, with increasing priorities of 2,
4, and 5, respectively.
• A user program begins at t=0. At t=10, a printer interrupt
occurs; user information is placed on the system stack and
execution continues at the printer interrupt service routine
(ISR).
• While this routine is still executing, at t=15, a
communications interrupt occurs. Because the
communications line has higher priority than the printer,
the interrupt is honored.
• The printer ISR is interrupted, its state is pushed onto the
stack, and execution continues at the communications ISR.
• While this routine is executing, a disk interrupt occurs (t
20). Because this interrupt is of lower priority, it is simply
held, and the communications ISR runs to completion.
Multiple Interrupts Example
• When the communications ISR is complete (t 25), the
previous processor state is restored, which is the execution
of the printer ISR.
• However, before even a single instruction in that routine
can be executed, the processor honors the higher priority
disk interrupt and control transfers to the disk ISR. Only
when that routine is complete (t=35) is the printer ISR
resumed.
• When that routine completes (t=40),control finally returns
to the user program.
• Refer to the figure
Example time sequence of multiple
interrupts
Connecting
• A computer consists of a set of components or modules of
three basic types (processor, memory, I/O) that
communicate with each other. In effect, a computer is a
network of basic modules.
• Thus, there must be paths for connecting the modules.
• The collection of paths connecting the various modules is
called the interconnection structure.All the units must
be connected
• Different type of connection for different type of unit
— Memory
— Input/Output
— CPU
Computer Modules
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Input/Output Connection(1)
• Similar to memory from computer’s
viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
—Send data to computer
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
• Receive addresses from computer
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
• The preceding list defines the data to be exchanged. The
interconnection structure must support the following types
of transfers:
• Memory to processor: The processor reads an
instruction or a unit of data from memory.
• Processor to memory: The processor writes a unit of
data to memory.
• I/O to processor:The processor reads data from an
I/O device via an I/O module.
• Processor to I/O: The processor sends data to the
I/O device.
• I/O to or from memory: For these two cases, an
I/O module is allowed to exchange data directly with
memory, without going through the processor, using
direct memory access (DMA).
What is a Bus?
• A communication pathway connecting two
or more devices
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels
Data Bus
• Carries data
—Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of performance
—8, 16, 32, 64 bit
• Because each line can carry only 1 bit at a time,
the number of lines determines how many bits
can be transferred at a time
• The width of the data bus is a key factor in
determining overall system performance.
• For example, if the data bus is 32 bits wide and
each instruction is 64 bits long, then the
processor must access the memory module twice
during each instruction cycle.
Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction
(data) from a given location in memory
• Bus width determines maximum memory
capacity of system
Control Bus
• Control and timing information
—Memory read/write signal
—Interrupt request
—Clock signals
• Typical control lines include following operations;
— Memory write: Causes data on the bus to be written
into the addressed location
— Memory read: Causes data from the addressed
location to be placed on the bus
— I/O write: Causes data on the bus to be output to the
addressed I/O port
— I/O read: Causes data from the addressed I/O port to
be placed on the bus
— Transfer ACK: Indicates that data have been accepted
from or placed on the bus
— Bus request: Indicates that a module needs to gain
control of the bus
— Bus grant: Indicates that a requesting module has
been granted control of the bus
— Interrupt request: Indicates that an interrupt is
pending
— Interrupt ACK: Acknowledges that the pending
interrupt has been recognized
— Clock: Is used to synchronize operations
— Reset: Initializes all modules
Bus Interconnection Scheme
Physical Realization of Bus Architecture
Physical Realization of Bus Architecture
• Physically, the system bus is actually a number of parallel
electrical conductors.
• In the classic bus arrangement, these conductors are metal
lines etched in a card or board (printed circuit board).
• The bus extends across all of the system components,
each of which taps into some or all of the bus lines.
• The classic physical arrangement is depicted in Figure.
• The bus consists of two vertical columns of conductors.
• At regular intervals along the columns, there are
attachment points in the form of slots that extend out
horizontally to support a printed circuit board.
• Each of the major system components occupies one or
more boards and plugs into the bus at these slots.
Problem
• Consider a hypothetical 32-bit microprocessor having 32-
bit instructions composed of two fields: the first byte
contains the opcode and the remainder the immediate
operand or an operand address.

a. What is the maximum directly addressable memory

capacity (in bytes)?

b. Discuss the impact on the system speed if the

microprocessor bus has
1. a 32-bit local address bus and a 16-bit local data bus
2. a 16-bit local address bus and a 16-bit local data bus.

c. How many bits are needed for the program counter and the
instruction register?
Solution
Problem
The hypothetical machine of Figure 3.4 also has two I/O
instructions:0011 Load AC from I/O 0111 Store AC to I/O
In these cases,the 12-bit address identifies a particular I/O device.
Show the program execution (using the format of Figure 3.5) for the
following program:
1.Load AC from device 5.
2.Add contents of memory location 940.
3.Store AC to device 6.
Assume that the next
value retrieved from
device 5 is 3 and
that location 940
contains a value of 2.
Solution