DIGITAL LOGIC DESIGN

SIII EE

LATCHES AND FLIP FLOPS

 Latch Vs Flip Flop
Latches and Flip Flops are almost
identical but
There is a difference between them
That is, ‘how they are triggered’ or
‘activated’
Remember
 Latch Vs Flip Flop
• Latches are ‘Level Triggered’ and
• Flip Flops are ‘Edge Triggered’

• Sub Types;
• Active High & Active Low Latches
• +ve edge trgrd Flip Flop & –ve edge trgrd F/F

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 Level Triggering & Edge Triggering
• A ‘pulse’ comprises of 4 parts;
• Low Level
• High Level
• Rising Edge (+ve edge)
• Falling Edge (-ve edge)
• See the following pulses comprising of these four parts;

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 Level Triggering & Edge Triggering (Contd)

• So, a Latch may be triggered on High Level and

• Another Latch may be triggered on Low Level
• But none of them are triggered on any of the Edges
• Similarly, a Flip Flop may trigger on +ve Edge and
• Another Flip Flop may trigger on -ve Edge
• Thus 1st type of Latch is called as ‘Active High Latch
• 2nd type of Latch is called as ‘Active Low Latch
• And 1st type of F/F is called as ‘+ve Edge Trgrd F/F’
• 2nd type of F/F is called as ‘-ve Edge Trgrd F/F’
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 EDGE TRIGGERED FLIP FLOPS

• Thus in Latches, changes in their outputs

or states occur during the Hi or Lo Level of
the clock pulse

• And in Flip Flops, changes in their outputs

or states occur at +ve or –ve transition of the
clock pulse.
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 EDGE TRIGGERED S-R FLIP FLOPS
• The S-R inputs of flip flops are synchronous inputs
because the input data is transferred to the output on
trailing edge of the clock pulse

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 EDGE TRIGGERED D-FLIP FLOP
The D flip flop is useful
when a single bit (1 or 0)
is to be stored.
• Example of +ve edge
trgrd F/F

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 EDGE TRIGGERED J-K FLIP FLOP

• The J-K flip flop is identical to S-R, D flip flop in 3

states; Set, Reset & No change condition operation

• The difference is that J-k flip flop has no invalid

condition

• Instead of ‘invalid condition’ here we get some ‘new’

features
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 WORKING OF EDGE TRIGGERED J-K FLIP
FLOP
We get an invalid condition
when both the inputs are
high in S-R flip flop but in J-
K this invalid state is
replaced by the TOGGLING

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 Truth Tables
• Task:
• Write complete Truth Tables of D & JK Flip
Flops covering all possibilities.

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 SYMBOLS
• Symbols of F/Fs

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 Symbols of D F/Fs
• +ve & -ve edge Triggered

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 Symbols of JK F/Fs
• +ve & -ve edge Triggered

• In the symbols of Latches ‘Arrow Head’ is not

present on Clock input

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 APPLICTIONS OF FLIP FLOPS
1. Counters of different types

2. Registers of different types

3. Memory devices etc

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