Electronics

PHY 234
Spring 2021

Dr. Muhammad Habib

Department of Physics
COMSATS University Islamabad
Applications of logic gates

 RS flip flop or a latch

 Clocked or gated flip flop
 Master slave flip flop
 JK flip flop
 T flip flop

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Applications of logic gates
Flip flop
 The basic flip-flop are also called binary or the R-S flip-flop (RSFF).
 A flip-flop is a bistable device/circuit.
 Both of its output states are stable.
 The circuit remains in a particular output state indefinitely until something is done to change the output
conditions.
 The circuit has
 It has two inputs named S and R (which stand for Set and Reset)
and outputs labeled Q and .
 Outputs (Q & ) of two NAND gates are feed back to the inputs of other gates.

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Applications of logic gates
 The four possible cases are summarized in the table.
 Flip flop working can be started with both R and S high and Q and
in one of the two stable states.
 Any change can be resume by making R or S low (logic 0).
 In case 1, when Q, = 0, 1 initially, then making S low changes
the outputs to Q, = 1, 0.
 Case 2 shows that if Q, = 1, 0 initially, then making
S low has no effect.
 Similarly, cases 3 and 4 show that making R low leaves the
outputs in the state Q, = 0, 1 regardless of the initial state.
 It can be summarized as the current output state tells us
which input was low last. If S was low last, then the output state will be
Q, = 1, 0. If R was low last, the output state will be Q, = 0, 1.

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Flip flop types
• There are a few other types of flip flops.

Clocked Flip flop

 This circuit is called the clocked or gated R-S flip-flop.
 Its main part consist of a simple RS flip flop.
 Another segment of two NAND gates is connected to the inputs of RS flip flop.
 Now the state are controlled and only changes when there will be a low input to change states.

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Clocked/ gated/ Synchronous S–R flip-flop

 It is easy to change the output at certain instant of time.

The output will only change when there will be a clock pulse signal along with RS input.
 The output will not change when the clock pulse is 0.
 When the output changes state with the positive edge of the pulse, it is
positive-triggered clock and when the output changes state with
the negative edge of the pulse, it is negative clock.
Equivalent circuit

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RS flip flop or a latch using NOR gates

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Flip flop types
Master-Slave flip flop
 A master-slave flip flop can be constructed with two separate flip flops
in which one will call master while other would serve as slave flip flop.
 We have mentioned earlier that output of flip flop will change
only when there would be a clock pulse at input.
 If there are multiple changes in the levels of the input/s S & R
during the time C is high, the outputs will also change multiple times.
 The process of isolating input changes from multiple output changes
during a single input clock signal, so that the state of the inputs S and R
at one instant of time will be read and saved, is done by constructing a Master-Slave flip flop.

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Flip flop types
Master-Slave flip flop
 A master-slave flip flop can be constructed with two separate flip flops
in which one will call master while other would serve as slave flip flop.
 We have mentioned earlier that output of flip flop will change
only when there would be a clock pulse at input.
 If there are multiple changes in the levels of the input/s S & R
during the time C is high, the outputs will also change multiple times.
 The process of isolating input changes from multiple output changes
during a single input clock signal, so that the state of the inputs S and R
at one instant of time will be read and saved, is done by constructing a Master-Slave flip flop.
 Master-slave flip flop can be constructed with the NOR gates.

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Master-Slave flip flop

Working of a master-slave flip flop

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Additional information

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Flip flop types
Simple RS flip flop exhibits
JK flip flop Invalid state with low inputs
 Why do we need to make JK flip flop ?
 If both inputs of Master-slave are High (logic 1) or
Low (logic 0) for RS flip flop then there will be
invalid or unpredictable state.

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Flip flop types
JK (Jack Kilby) flip flop
 Why do we need to make JK flip flop ?
 If both inputs of Master-slave are High (logic 1) or
Low (logic 0) for RS flip flop then there will be
invalid or unpredictable state.
 One way to deal with this problem is to add
feedback lines from the both outputs to the inputs.
 A clocked flip flop with such kind of feedback formation
is called a JK flip flop and its inputs are renamed from
R S to J K.

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Flip flop types
T flip flop
 T flip flop is a single input version of the JK flip flop.
 If both inputs (J & K) of the JK flip flop are tied together then T flip flop is formed.
 Input T denotes toggling.
 Whatever the state is present at the output, T flip flop will complement
it's output when T input is high (logic 1) along with the clock pulse.
 In other word T flip flop inverts its outputs whenever
T input is triggered.

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Thanks for your attention please.

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