Unit 2

Additional Traditional Logic Design Topics

Dr. Khursheed Aurangzeb

1
Propagation Delay and Timing

2
Propagation Delay
 Propagation delay is the time for a change on an input
of a gate to propagate to the output.
 Delay is usually measured at the 50% point with
respect to the H and L output voltage levels.
 High-to-low (tPHL) and low-to-high (tPLH) output signal
changes may have different propagation delays.
 High-to-low (HL) and low-to-high (LH) transitions are
defined with respect to the output, not the input.
 An HL input transition causes:
• an LH output transition if the gate inverts and
• an HL output transition if the gate does not invert.

3
Propagation Delay (continued)

 Propagation delays measured at the midpoint between the L

and H values.
 tPLH = The low-to-high propagation time.
 tPHL = The high-to-low propagation time.
 tpd = Propagation delay = Max(tPLH , tPHL)

4
 Propagation Delay Example
 Find tPHL, tPLH and tpd for the signals given
IN (volts)
OUT (volts)

1.1 ns

1.4 ns  tpd =1.4 ns

t (ns)
1.0 ns per division 5
Flip-Flop Timing Parameters
 ts - setup time twH  twH,min
C twL twL,min
 th - hold time ts th
S /R
 tw - clock
tp-,min
pulse width t p-,max
Q
 tpx - propa- (a) Pulse-triggered (positive pulse)
gation delay twH t wH,min
• tPHL - High-to-C twL  twL,min
Low ts th
• tPLH - Low-to-D
High t p-,min
t p-,max
• tpd - max (tPHL,
Q
tPLH)
(b) Edge-triggered (negative edge)
6
Flip-Flop Timing Parameters
 ts - setup time
• Master-slave - Equal to the width of the triggering
pulse
• Edge-triggered - Equal to a time interval that is
generally much less than the width of the triggering
pulse
 th - hold time - Often equal to zero
 tpx - propagation delay
• Same parameters as for gates except
• Measured from clock edge that triggers the output
change to the output change
7
Circuit and System Level Timing
 Consider a system
comprised of ranks
D Q D Q
C Q' C Q'

of flip-flops D Q D Q

connected by logic: C Q' C Q'

 If the clock period is D Q

C Q'
D Q
C Q'

too short, some D Q D Q

data changes will not C Q' C Q'

propagate through the D Q D Q

C Q' C Q'

circuit to flip-flop
inputs before the setup
CLOCK CLOCK

time interval begins

8
Circuit and System Level Timing
 New Timing Components
• tp - clock period - The interval between occurrences
of a specific clock edge in a periodic clock

• tpd,COMB - total delay of combinational logic along the

path from flip-flop output to flip-flop input

• tslack - extra time allowed in the clock period in

beyond that required by the path
 Must be greater than or equal to zero on all paths for
correct operation

9
Circuit and System Level Timing
 Timing components along a path from flip-flop
to flip-flop
tp

C
tpd,FF tpd,COMB ts tslack
(a) Edge-triggered (positive edge)

tp

C
tpd,FF tpd,COMB tslack ts
(b) Pulse-triggered (negative pulse)

10
Circuit and System Level Timing
 Timing Equations
tp = tslack + (tpd,FF + tpd,COMB + ts)

• For tslack greater than or equal to zero,

tp ≥ max (tpd,FF + tpd,COMB + ts)
for all paths from flip-flop output to flip-flop input

 Can be calculated more precisely by using tPHL

and tPLH values instead of tpd values, but
requires consideration of inversions on paths
11
Example 1: Calculation of Allowable tpd,COMB

 Compare the allowable combinational delay for a

specific circuit:
a) Using edge-triggered flip-flops
b) Using master-slave flip-flops

 Parameters
• tpd,FF(max) = 1.0 ns
• ts(max) = 0.3 ns for edge-triggered flip-flops
• ts = twH = 1.0 ns for master-slave flip-flops
• Clock frequency = 250 MHz

12
Example 1: Calculation of Allowable tpd,COMB

 Calculations: tp = 1/clock frequency = 4.0 ns

• Edge-triggered: 4.0 ≥ 1.0 + tpd,COMB + 0.3, tpd,COMB ≤ 2.7 ns
• Master-slave: 4.0 ≥ 1.0 + tpd,COMB + 1.0, tpd,COMB ≤ 2.0 ns

 Comparison: Suppose that for a gate, average tpd =

0.3 ns
• Edge-triggered: Approximately 9 gates allowed on a path
• Master-slave: Approximately 6 to 7 gates allowed on a path

13
Example 2: Clock Period & Frequency
Calculations
 Parameters
• tpd,FF(max) = 0.2 ns
• ts(max) = 0.1 ns for edge-triggered flip-flops
• tpd,COMB (max) = 1.3 ns
• tp = 1.5 ns
 Solution
• tp = tslack + (tpd,FF + tpd,COMB + ts)
•  1.5 = tslack + (0.2 + 1.3 + 0.1)
•  tslack = -0.1 ns
• tslack has to be greater than or equal to zero for the longest path
•  tp is too small
•  tp  tp, min = 1.6 ns
• fmax = 1 / 1.6 ns = 625 MHz
14
Registers and Counters

15
Registers
 Register – a collection of binary storage
elements
 In theory, a register is sequential logic
which can be defined by a state table
 More often, think of a register as storing
a vector of binary values
 Frequently used to perform simple data
storage and data movement and
processing operations

16
Example: 2-bit Register
 How many states are there? A1
Y1
In1 D Q
 How many input combinations?
C
Output combinations? A0
 What is the output function? In0 D Q Y0

 What is the next state function? CP C

 Moore or Mealy? Current Next State Output
State A1(t+1) A0(t+1) (=A1 A0)
For In1 In0 =
A1 A0 00 01 10 11 Y1 Y0
0 0 00 01 10 11 0 0
0 1 00 01 10 11 0 1
1 0 00 01 10 11 1 0
1 1 00 01 10 11 1 1
 What are the quantities above for an n-bit register?

17
Register Design Models
 Due to the large numbers of states and input
combinations as n becomes large, the state
diagram/state table model is not feasible!
 What are methods we can use to design
registers?
• Add predefined combinational circuits to registers
 Example: To count up, connect the register flip-flops to an
incrementer
• Design individual cells using the state diagram/state
table model and combine them into a register
 A 1-bit cell has just two states
 Output is usually the state variable

18
 Register Storage
 Expectations:
• A register can store information for multiple clock cycles
• To “store” or “load” information should be controlled by a signal
 Reality:
• A D flip-flop register loads information on every clock cycle
 Realizing expectations:
• Use a signal to block the clock to the register,
• Use a signal to control feedback of the output of the register back to
its inputs, or
• Use other SR or JK flip-flops, that for (0,0) applied, store their state
 Load is a frequent name for the signal that controls
register storage and loading
• Load = 1: Load the values on the data inputs
• Load = 0: Store the values in the register

19
Registers with Load-Controlled
Feedback
 A more reliable way to selectively load a register:
• Run the clock continuously, and
• Selectively use a load control to change the register contents.
 Example: 2-bit register
with Load Control: 2-to-1 Multiplexers
 For Load = 0,
loads register contents
(hold current values)
 For Load = 1, A1
D Q Y1
loads input values Load
(load new values) In1 C
 Hardware more complex
than clock gating, but A0
D Q Y0
free of timing problems C
In0
Clock 20
 Register Notation
R 76543210

15 8 7 0 15 0
PC(H) PC(L) R2

 Letters and numbers – denotes a register (ex. R2, PC, IR)

 Parentheses ( ) – denotes a range of register bits (ex. R1(1),
PC(7:0), PC(L))
 Arrow () – denotes data transfer (ex. R1  R2, PC(L) 
R0)
 Comma – separates parallel operations
 Brackets [ ] – Specifies a memory address (ex. R0 
M[AR], R3  M[PC] )

21
Conditional Transfer
 If (K1 =1) then (R2  R1) K
1
is shortened to
n Load
K1: (R2  R1) R1 R2
where K1 is a control
variable specifying a
conditional execution Clock
of the microoperation.
  Clock

K1
Transfer Occurs Here
No Transfers Occur Here

22
Microoperations
 Logical Groupings:
• Transfer - move data from one register to another
• Arithmetic - perform arithmetic on data in registers
• Logic - manipulate data or use bitwise logical operations
• Shift - shift data in registers

Arithmetic operations Logical operations

+ Addition  Logical OR
– Subtraction  Logical AND
* Multiplication  Logical Exclusive OR
/ Division  Not

23
Example Microoperations
 Add the content of R1 to the content of
R2 and place the result in R1.
R1 R1 + R2
 Multiply the content of R1 by the content
of R6 and place the result in PC.
PC  R1 * R6
 Exclusive OR the content of R1 with the
content of R2 and place the result in R1.
R1  R1  R2

24
Example Microoperations (Continued)

 Take the 1's Complement of the contents

of R2 and place it in the PC.
 PC  R2
 On condition K1 OR K2, the content of
R1 is Logic bitwise Ored with the content
of R3 and the result placed in R1.
 (K1 + K2): R1  R1  R3
 NOTE: "+" (as in K1 + K2) and means
“OR.” In R1  R1 + R3, + means “plus.”

25
Control Expressions
 The control expression for
an operation appears to the
left of the operation and is
separated from it by a colon
 Control expressions specify  Variable K1 enables the add
the logical condition for the
operation to occur
 Control expression values
of:
• Logic "1" -- the operation
occurs.
• Logic "0" -- the operation is
does not occur.
 Example:
X K1 : R1  R1 + R2
X K1 : R1  R1 + R2 + 1
or subtract operation.
 If X =0, then X =1 so
X K1 = 1, activating the
addition of R1 and R2.
 If X = 1, then X K1 = 1,
activating the addition of R1
and the two's complement of
R2 (subtract).
26
Arithmetic Microoperations
 From Symbolic Designation Description
Table R0 ¬ R1 + R2 Addition
7-3: R0 ¬ R1 Ones Complement
R0 ¬ R1 + 1 Two's Complement
R0 ¬ R2 + R1 + 1 R2 minus R1 (2's Comp)
R1 ¬ R1 + 1 Increment (count up)
R1 ¬ R1 – 1 Decrement (count down)
 Note that any register may be specified for
source 1, source 2, or destination.
 These simple microoperations operate on the
whole word

27
Logical Microoperations
 From Table 7-4:

Symbolic Description
Designation
R0 ¬ R1 Bitwise NOT
R0 ¬ R1 Ú R2 Bitwise OR (sets bits)
R0 ¬ R1 Ù R2 Bitwise AND (clears bits)
R0 ¬ R1 Å R2 Bitwise EXOR (complements bits)

28
Logical Microoperations (continued)

 Let R1 = 10101010,
and R2 = 11110000
 Then after the operation, R0 becomes:

29
Shift Microoperations
 From Table 7-5: Symbolic Description
 Let R2 = 11001001 Designation
 Then after the R1 ¬ sl R2 Shift Left
operation, R1 R1 ¬ sr R2 Shift Right
becomes: R1 Operation
10010010 R1 ¬ sl R2
01100100 R1 ¬ sr R2

 Note: These shifts "zero fill". Sometimes a separate

flip-flop is used to provide the data shifted in, or to
“catch” the data shifted out.
 Other shifts are possible (rotates, arithmetic) (see Chapter
10).
30
Multiplexer-Based Transfers
 Multiplexers connected to register inputs produce
flexible transfer structures (Note: Clocks are omitted
for clarity)
 The transfers are: K1: R0  R1
Load K2×K1: R0  R2
K2
R2
K1

S Load
n
0 n
MUX R0
n
Load 1
R1

31
 Shift Registers
 Shift Registers move data laterally within the register toward
its MSB or LSB position
 In the simplest case, the shift register is simply a set of
D flip-flops connected in a row like this:

 Data input, In, is called a serial input or the shift right input.
 Data output, Out, is often called the serial output.
 The vector (A, B, C, Out) is called the parallel output.

32
 Shift Registers (continued)
 The behavior of the B
In A C Out
serial shift register DQ DQ DQ DQ
is given in the listing
on the lower right
 T0 is the register
Clock CP
state just before
the first clock CP In A B C Out
pulse occurs T0 0 ? ? ? ?
 T1 is after the T1 1 0 ? ? ?
first pulse and T2 1 1 0 ? ?
before the second. T3 0 1 1 0 ?
 Initially unknown T4 1
states are denoted by “?” T5 1
 Complete the last three T6 1
rows of the table

33
Parallel Load Shift Registers
D D
 By adding a mux A B

A B
between each shift register
stage, data can be IN D
Q
D
Q
shifted or loaded
 If SHIFT is low, SHIFT
A and B are CP
replaced by the data on DA and DB lines, else data shifts
right on each clock.
 By adding more bits, we can make n-bit parallel load
shift registers.
 A parallel load shift register with an added “hold”
operation that stores data unchanged is given in Figure 7-
10 of the text.

34
Shift Registers with Additional
Functions
 By placing a 4-input multiplexer in front of each D
flip-flop in a shift register, we can implement a circuit
with shifts right, shifts left, parallel load, hold.
 Shift registers can also be designed to shift more than a
single bit position right or left
 Shift registers can be designed to shift a variable
number of bit positions specified by a variable called a
shift amount.

35
 Serial Adder
Load/Right Shift Registers
 The circuit shown uses two shift
registers for operands A(3:0) Serial
and B(3:0). In A

 A full adder, and one more FA

A3 A2 A1 A0 B
flip flop (for the carry) is used Parallel Load
Sum
Cin
to compute the sum. Serial Cout
 The result is stored in the In

A register and the final B3 B2 B1 B0

carry in the flip-flop Parallel Load Q D
(Clock and Load/Shift CP
 With the operands and the Control not shown)

result in shift registers, a tree of full adders can be

used to add a large number of operands. Used as a
common digital signal processing technique.

36
Counters
 Counters are sequential circuits which "count"
through a specific state sequence. They can count up,
count down, or count through other fixed sequences.
Two distinct types are in common usage:
 Ripple Counters
• Clock connected to the flip-flop clock input on the LSB bit
flip-flop
• For all other bits, a flip-flop output is connected to the clock
input, thus circuit is not truly synchronous!
• Output change is delayed more for each bit toward the MSB.
• Resurgent because of low power consumption
 Synchronous Counters
• Clock is directly connected to the flip-flop clock inputs
• Logic is used to implement the desired state sequencing
37
Ripple Counter
 How does it work? D A
• When there is a positive
Clock CR
edge on the clock input
of A, A complements
• The clock input for flip- D B

flop B is the complemented CR

output of flip-flop A Reset

• When flip A changes

from 1 to 0, there is a CP
positive edge on the
clock input of B A
causing B to B
complement
0 1 2 3 0 1
38
Ripple Counter (continued)
 The arrows show the
cause-effect relation- CP
ship from the prior
A
slide =>
 The corresponding B
sequence of states => 0 1 2 3 0 1
(B,A) = (0,0), (0,1), (1,0), (1,1), (0,0), (0,1), …
 Each additional bit, C, D, …behaves like bit B,
changing half as frequently as the bit before it.
 For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1),
(1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), …
39
Ripple Counter (continued)
 These circuits are called ripple counters because
each edge sensitive transition (positive in the
example) causes a change in the next flip-flop’s
state.
 The changes “ripple” upward through the
chain of flip-flops, i. e., each transition occurs
after a clock-to-output delay from the stage
before.
 To see this effect in detail look at the waveforms
on the next slide.

40
 Ripple Counter (continued)
 Starting with C = B = A = 1, equivalent to
(C,B,A) = 7 base 10, the next clock increments
the count to (C,B,A) = 0 base 10. In fine timing
detail:
• The clock to output delay tPHL
CP
tPHL causes an increasing
delay from clock edge for A tPHL
each stage transition.
• Thus, the count “ripples” tpHL
B
from least to most
significant bit.
• For n bits, total worst caseC
delay is n tPHL.

41
Synchronous Counters
 To eliminate the "ripple" effects, use a common clock
for each flip-flop and a combinational circuit to
generate the next state.
 For an up-counter,
use an incrementer =>
Incre-
menterS3 D3 Q3
A3
A2 S2 D2 Q2
A1 S1 D1 Q1
A0 S0 D0 Q0

Clock

42
 Synchronous Counters
(continued)
 Internal details => Incrementer
D Q0
 Internal Logic Count enable EN
C
• XOR complements each bit
• AND chain causes complement
D Q1
of a bit if all bits toward LSB
C
from it equal 1
 Count Enable
• Forces all outputs of AND D Q2

chain to 0 to “hold” the state C

 Carry Out
• Added as part of incrementer D Q3
• Connect to Count Enable of C

additional 4-bit counters to Carry

form larger counters output CO
Clock
(a) Logic Diagram-Serial Gating
43
Other Counters
 See text for:
• Down Counter - counts downward instead of upward
• Up-Down Counter - counts up or down depending on value
a control input such as Up/Down
• Parallel Load Counter - Has parallel load of values
available depending on control input such as Load
 Divide-by-n (Modulo n) Counter
• Count is remainder of division by n; n may not be a
power of 2 or
• Count is arbitrary sequence of n states specifically
designed state-by-state
• Includes modulo 10 which is the BCD counter

44
Counter with Parallel Load
Load
 Add path for input data
Count
• enabled for Load = 1 D0 D Q0

 Add logic to: C

• disable count logic for Load = 1

• disable feedback from outputs
for Load = 1 D1 D Q1

• enable count logic for Load = 0 C

and Count = 1
 The resulting function table:
D2 D Q2

Load Count Action C

0 0 Hold Stored Value

0 1 Count Up Stored Value D3 D Q3

1 X Load D
C

Carry
Output CO
Clock
45
Design Example: Synchronous
BCD
 Use the sequential logic model to design a synchronous
BCD counter with D flip-flops
 State Table => Current State Next State
 Input combinations Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1
1010 through 1111 0 0 0 0 0 0 0 1
are don’t cares 0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0

46
Synchronous BCD (continued)
 Use K-Maps to two-level optimize the next state
equations and manipulate into forms containing XOR
gates:
D1 = Q1
D2 = Q2 + Q1Q8
D4 = Q4 + Q1Q2
D8 = Q8 + (Q1Q8 + Q1Q2Q4)
 The logic diagram can be draw from these equations
• An asynchronous or synchronous reset should be added
 What happens if the counter is perturbed by a power
disturbance or other interference and it enters a state
other than 0000 through 1001?

47
 Synchronous BCD (continued)
 Find the actual values of the six next states for the
don’t care combinations from the equations
 Find the overall state diagram to assess behavior for
the don’t care states (states in decimal)
0
Present State Next State 9 1
Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 14
1 0 1 0 1 0 1 1 2
8
1 0 1 1 0 1 1 0 15
12
1 1 0 0 1 1 0 1
1 1 0 1 0 1 0 0 7 11 13 3
1 1 1 0 1 1 1 1 10
6 4
1 1 1 1 0 0 1 0
5
48
 Another Example
 Circuit for a 4-bit shift register with a Parallel
Load, known as Parallel-Access shift register:

Chapter 6 - Part 1 49
A Synchronous 3-Bit (Up)Counter Using T Flip-
Flops
 We know that for a T flip-flop
Clock cycle Q2 Q1 Q0 (Q+=T^Q).
Q1 changes Assume the count is initially
0 0 0 0 set to 0.
1 0 0 1 Q2 changes Observe the following pattern:
2 0 1 0 1. Bit Q0 changes on each
3 0 1 1 clock cycle
4 1 0 0 2. Bit Q1 changes only when
5 1 0 1 bit Q0 = 1.
6 1 1 0 3. Bit Q2 changes only when both
7 1 1 1 Q1 and Q0 are equal
8 0 0 0 to 1.  THIS MEANS:
For n-bit up-counter, a flip-flop
changes its state only when all
preceding FFs are in the state
Thus, the T inputs are : T0 = 1, T1 = Q0 , T2 = Q0QQ1,=…,1. Tn = Q0Q1…Qn-1
Synchronous (Up)Counter Using T Flip-Flops - 2

1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q

(a) Circuit Diagram

Clock

Q0

Q1

Q2

Q3

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing Diagram

Adding an Enable and Clear_n (or Resetn) Capability

Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear_n
Same Synchronous Counter Using D Flip-Flops

 The count is indicated by the

FF outputs: Q3Q2Q1Q0.

If Enable = 1, then the D

inputs (D = T xor Q ) are:

• D0 = Q0 xor 1 = Q’0
• D1 = Q1 xor Q0
• D2 = Q2 xor Q1Q0
• D3 = Q3 xor Q2Q1Q0
• Di = Qi xor Qi-1Qi-2…Q1Q0
An Example 4-Bit Synchronous Counter Using
D FFs
A Faster Version of the 4-Bit Synchronous
Counter
A Synchronous Counter Using D Flip-Flops with Parallel Load

A control input or selector, Load,

is used to choose the mode of
Operation:

 The circuit counts when

Load = 0.

 A new initial value = D3D2D1D0

is loaded/stored into the counter
when Load = 1.
Other Counters – Ring Counter

Operation of this counter is initialized by injecting a 1 into the first stage (or flip flop):
 Use the Start control signal, which presets the left-most FF to 1 and clears
others to 0.

Start is an asynchronous signal.

Possible sequence of numbers is: 1000, 0100, 0010, 0001 (then, it repeats).
 This is known as one-hot-code because there is a single 1 and the rest of bits
are 0 in each output code.
Other Counters – Johnson Counter

 We take the Q’ output of the last FF and feed it back to the first FF. The
generated counting sequence has a length, cycle, or period of 2n (= 8 for n =
4).
 Proper initialization of the counter is necessary to generate the desired
counting sequence. This is done by resetting all FFs via the signal Reset_n.
 Sequence of a 4-bit Johnson counter is: 0000, 1000, 1100,1110, 1111, 0111,
0011, 0001, then 0000, and so on.
Other Counters – Linear Feedback Shift Register
(LFSR)

 A Linear-Feedback Shift Register (LFSR) is a type of

circuit that generates a counting sequence of pseudo-
random numbers that repeats after 2n – 1 cycles, where n is
the number of flip flops in the LFSR.
 It takes a parallel load input R[ ] when selector L is high,
else: Q0 ← Q2, Q1 ← Q0 xor Q2, and Q2 ← Q1.
 What is the generated sequence of numbers in this
case, assuming 0012 is the first number?
 Sequence generated: 001, 110, 011, 111, 101, 100, 010, 001, ….
 Length (or period) of sequence is 7 (= 23 – 1).
 Draw its circuit
Comparison of two different implementation of LFSR
Memory Essentials

61
Memory Definitions
 Memory ─ A collection of storage cells together with
the necessary circuits to transfer information to and
from them.
 Memory Organization ─ the basic architectural
structure of a memory in terms of how data is accessed.
 Random Access Memory (RAM) ─ a memory
organized such that data can be transferred to or from
any cell (or collection of cells) in a time that is not
dependent upon the particular cell selected.
 Memory Address ─ A vector of bits that identifies a
particular memory element (or collection of elements).

62
Memory Definitions (Continued)
 Typical data elements are:
• bit ─ a single binary digit
• byte ─ a collection of eight bits accessed together
• word ─ a collection of binary bits whose size is a
typical unit of access for the memory. It is typically
a power of two multiple of bytes (e.g., 1 byte, 2
bytes, 4 bytes, 8 bytes, etc.)
 Memory Data ─ a bit or a collection of bits to
be stored into or accessed from memory cells.
 Memory Operations ─ operations on memory
data supported by the memory unit. Typically,
read and write operations over some data
element (bit, byte, word, etc.).
63
Memory Organization
 Organized as an indexed array of words. Value of the
index for each word is the memory address.
 Often organized to fit the needs of a particular
computer architecture. Some historically significant
computer architectures and their associated memory
organization:
• Digital Equipment Corporation PDP-8 – used a 12-bit address
to address 4096 12-bit words.
• IBM 360 – used a 24-bit address to address 16,777,216 8-bit
bytes, or 4,194,304 32-bit words.
• Intel 8080 – (8-bit predecessor to the 8086 and the current
Intel processors) used a 16-bit address to address 65,536 8-bit
bytes.

64
 Memory Block Diagram
 A basic memory system is n Data Input Lines

shown here: n

 k address lines are k Address Lines Memory

Unit
decoded to address 2k k
2k Words
words of memory. 1 n Bits per Word
Read
 Each word is n bits. 1
 Read and Write are single Write
control lines defining the n
simplest of memory
n Data Output Lines
operations.

65
 Memory Organization Example
 Example memory
contents: Memory Address Memory
• A memory with 3 Binary Decimal Content
000 0 10001111
address bits & 8
001 1 11111111
data bits has:
010 2 10110001
• k = 3 and n = 8 so
011 3 00000000
23 = 8 addresses 100 4 10111001
labeled 0 to 7. 101 5 10000110
• 23 = 8 words of 8-bit 11 0 6 00110011
data 111 7 11001100

66
Basic Memory Operations
 Memory operations require the following:
• Data ─ data written to, or read from, memory as
required by the operation.
• Address ─ specifies the memory location to operate
on. The address lines carry this information into
the memory. Typically: n bits specify locations of 2n
words.
• An operation ─ Information sent to the memory and
interpreted as control information which specifies
the type of operation to be performed. Typical
operations are READ and WRITE. Others are
READ followed by WRITE and a variety of
operations associated with delivering blocks of data.
Operation signals may also specify timing info.
67
Basic Memory Operations
(continued)
 Read Memory ─ an operation that reads a data value
stored in memory:
• Place a valid address on the address lines.
• Wait for the read data to become stable.
 Write Memory ─ an operation that writes a data value to
memory:
• Place a valid address on the address lines and valid data on the
data lines.
• Toggle the memory write control line

68
RAM Integrated Circuits
 Types of random access memory
• Static – information stored in latches
• Dynamic – information stored as electrical charges
on capacitors
 Charge “leaks” off
 Periodic refresh of charge required
 Dependence on Power Supply
• Volatile – loses stored information when power
turned off
• Non-volatile – retains information when power
turned off

69
Memory Operation Timing
 Most basic memories are asynchronous
• Storage in latches or storage of electrical charge
• No clock
 Controlled by control inputs and address
 Timing of signal changes and data observation is critical to the
operation
 Read timing:
20 ns
Clock T1 T2 T3 T4 T1

Address Address valid

Memory
enable
Read/
Write
Data Data valid
output
65 ns
Read cycle
Chapter 8 70
Memory Operation Timing
 Write timing:
20 ns

Clock T1 T2 T3 T4 T1

Address Address valid

Memory
enable
Read/
Write
Data
input Data valid

75 ns
Write cycle
 Critical times measured with respect to edges of write pulse (1-0-1):
• Address must be established at least a specified time before 1-0 and held
for at least a specified time after 0-1 to avoid disturbing stored contents
of other addresses
• Data must be established at least a specified time before 0-1 and held for
at least a specified time after 0-1 to write correctly

Chapter 8 71
 Static RAM  Cell
 Array of storage cells used to implement static
RAM Select

 Storage Cell
• SR Latch B C
S Q
• Select input for
control C
R Q
• Dual Rail Data B
RAM cell
Inputs B and B
• Dual Rail Data
Outputs C and C

72
 Static RAM  Bit Slice
 Represents all circuitry that is required for 2n
Word Select

1-bit words select

0
B C
X

• Multiple RAM cells

S Q

C Word
X
B R Q select

• Control Lines: R A M cell 0

R A M cell

Word
 Word select i select
1

– one for each word Word

select
Select R A M cell

2n 2 1
 Read / Write X Word
S Q
select
 Bit Select X
2n 2 1
R A M cell
R Q

• Data Lines: R A M cell

R ead/Write
logic

 Data in D ata in
S Q D ata out
 Data out D ata in R ead/
Write
Bit
select
R Q

(b) Symbol

Write logic
R ead logic D ata out
R ead/ Bit
Write select
(a) Logic diagram
73
 2n-Word  1-Bit RAM IC
 To build a RAM IC
4-to-16 Word select
Decoder 0
A3 A3 23 1
from a RAM slice, A2 A2 2
2
3
RAM cell
2
we need: A1 A1 21
4
5

• Decoder  decodes A0 A0 20
6
7
RAM cell

the n address lines to 16 x 1

RAM
8
9

2n word select lines Data Data

10
11
input output
12
13

• A 3-state buffer  Read/ 14

15
Write
on the data output enable
Memory RAM cell

permits RAM ICs to Read/Write

(a) Symbol
be combined into a
logic

RAM with c  2n words

Data input Data in
Data out Data
output
Read/ Bit
Write select

Read/Write
Chip select
(b) Block diagram
74
Cell Arrays and Coincident Selection

 Memory arrays can be very large

• Large decoders
• Large fanouts for the bit lines
• The decoder size and fanouts can be reduced by
approximately by using a coincident selection in
a 2-dimensional array
• Uses two decoders, one for words and one for bits
• Word select becomes Row select
• Bit select becomes Column select
 See next slide for example
• A3 and A2 used for Row select
• A1 and A0 for Column select

75
Cell Arrays and Coincident Selection
Row decoder
2-to-4
Decoder 0
A3 21
RAM cell RAM cell RAM cell RAM cell
0 1 2 3
A2 20
1

Row RAM cell RAM cell RAM cell RAM cell

select 4 5 6 7
2

RAM cell RAM cell RAM cell RAM cell

8 9 10 11

RAM cell RAM cell RAM cell RAM cell

12 13 14 15

Read/Write Read/Write Read/Write Read/Write

logic logic logic logic

Data in Data in Data in Data in

Data out Data out Data out Data out
Read/ Bit Read/ Bit Read/ Bit Read/ Bit
Write select Write select Write select Write select
Data input
Read/Write

X X X X
Column select Data
0 1 2 3 output
Column 2-to-4 Decoder
decoder with enable
21 20 Enable

A1 A0
Chip select 76
RAM ICs with > 1 Bit/Word
 Word length can be quite high.
 To better balance the number of words
and word length, use ICs with > 1
bit/word

 Example
• 2 Data input bits
• 2 Data output bits
• Row select selects 4 rows
• Column select selects 2 pairs of columns

77
Block Diagram of an 8×2 RAM
Row decoder
2-to-4
Decoder 0
A2 21
RAM cell RAM cell RAM cell RAM cell
0 1 2 3
A1 20
1

Row RAM cell RAM cell RAM cell RAM cell

select 4 5 6 7
2

RAM cell RAM cell RAM cell RAM cell

8 9 10 11

RAM cell RAM cell RAM cell RAM cell

12 13 14 15

Read/Write Read/Write Read/Write Read/Write

logic logic logic logic

Data in Data in Data in Data in

Data out Data out Data out Data out
Read/ Bit Read/ Bit Read/ Bit Read/ Bit
Write select Write select Write select Write select
Data input 0
Data input 1
Read/Write
Data
X X Output 0
Column select
Data
0 1 X X Output 1
1-to-2 Decoder
Column
decoder with enable
20 Enable

A0 Chip select
78
Making Larger Memories
 Using the CS lines, we
can make larger
memories from smaller
ones by tying all
address, data, and R/W
lines in parallel, and
using the decoded
higher order address
bits to control CS.
 Using the 4-Word by 1-
Bit memory from
before, we construct a
16-Word by
1-Bit memory.  

79
Making Wider Memories
 To construct wider
memories from narrow
ones, we tie the address
and control lines in
parallel and keep the data
lines separate.
 For example, to make a 4-
word by 4-bit memory
from 4, 4-word by 1-bit
memories  
 Note: Both 16x1 and 4x4
memories take 4-chips
and hold 16 bits of data.

Chapter 8 80
Block Diagram of a 256K×8
RAM
Address
Input
Lines Lines 0 -15 Data 0 - 65535
17 16
64K × 8 RAM
16 8
2-to-4 Decoder DATA
Memory Enable EN
3 2 1 0 ADRS 
CS
Read/ Write R/W

65536- 131071
64K × 8 RAM
DATA
ADRS 
CS
R/W

131072 - 196607
64K × 8 RAM
DATA
ADRS 
CS
R/W

196608 - 262143
64K × 8 RAM
DATA
ADRS 
8
CS
R/W Output Data
Chapter 8 81
Block Diagram of a 64K×16
RAM
16 Input Data Lines

8 8

16
Address

64K × 8 RAM 64K × 8 RAM

8 8
DATA DATA
16  16 
ADRS ADRS
Chip Select CS CS
Read / Write R/W R/W

8 8

16 Output Data Lines

Chapter 8 82
 Block Diagram of a 256K×16
RAM
Address 16 Input Data Lines
8 8
Lines Lines 0 -15
17 16
64K × 8 RAM 64K × 8 RAM
16
2-to-4 Decoder DATA DATA
Memory Enable EN
3 2 1 0 ADRS  ADRS 
CS CS
Read/ Write R/W R/W

64K × 8 RAM 64K × 8 RAM

DATA DATA
ADRS  ADRS 
CS CS
R/W R/W

64K × 8 RAM 64K × 8 RAM

DATA DATA
ADRS  ADRS 
CS CS
R/W R/W

64K × 8 RAM 64K × 8 RAM

DATA DATA
ADRS  ADRS 
CS CS
R/W R/W
8 8
16 Output Data Lines Chapter 8 83
Dynamic RAM (DRAM)
 Basic Principle: Storage of information
on capacitors.
 Charge and discharge of capacitor to
change stored value
 Use of transistor as “switch” to:
• Store charge
• Charge or discharge
 See next slide for circuit, hydraulic
analogy, and logical model.

Chapter 8 84
 Dynamic RAM (continued)
Select

To Pump
Stored 1 Stored 0
T
B
C
DRAM cell
(a) (b) (c)

Write 1 Write 0
Select

(d) (e)
B D Q C
Read 1 Read 0
C DRAM cell
model

(h) (f) (g)

Chapter 8 85
 Dynamic RAM - Bit Slice
 C is driven by 3-state Word
select
0
Select

drivers B
D Q
C

 Sense amplifier is used C D R A M cell

model
Word
select
0

to change the small Word

D R A M cell

voltage change on C
select
1
Select D R A M cell

into H or L 2- 1

 In the electronics, B,
D Q
2- 1
C D R A M cell

C, and the sense model D R A M cell

R ead/Write

amplifier output are logic

connected to make
D ata in
Sense
amplifier D ata out
D ata in R ead/ Bit

destructive read into

Write select

non-destructive read
(b) Symbol

Write logic
Read logic D ata out
Bit
Read/
select
Write
(a) Logic diagram

Chapter 8 86
Programmable Implementation
Technologies

87
Why Programmable Logic?
 Facts:
• It is most economical to produce an IC in large
volumes
• Many designs required only small volumes of ICs
 Need an IC that can be:
• Produced in large volumes
• Handle many designs required in small volumes
 A programmable logic part can be:
• made in large volumes
• programmed to implement large numbers of
different low-volume designs

88
Programmable Logic - More Advantages
 Many programmable logic devices are field-
programmable, i. e., can be programmed outside of the
manufacturing environment
 Most programmable logic devices are erasable and
reprogrammable.
• Allows “updating” a device or correction of errors
• Allows reuse the device for a different design - the ultimate in
re-usability!
• Ideal for course laboratories
 Programmable logic devices can be used to prototype
design that will be implemented for sale in regular ICs.
• Complete Intel Pentium designs were actually prototyped with
specialized systems based on large numbers of VLSI
programmable devices!
89
Technology Characteristics
 Permanent - Cannot be erased and reprogrammed
 Fuse
 Antifuse

 Reprogrammable:
• Volatile - Programming lost if chip power lost
 Single-bit storage element
• Non-Volatile
 Erasable
 Electrically erasable
 Flash (as in Flash Memory)

90
Programmable Configurations
 Read Only Memory (ROM) - a fixed array of AND gates and a
programmable array of OR gates

 Programmable Array Logic (PAL)Ò - a programmable array of

AND gates feeding a fixed array of OR gates.

 Programmable Logic Array (PLA) - a programmable array of

AND gates feeding a programmable array of OR gates.

 Complex Programmable Logic Device (CPLD) /Field-

Programmable Gate Array (FPGA) - complex enough to be
called “architectures” - See VLSI Programmable Logic Devices
reading supplement

PAL is a registered trademark of Lattice Semiconductor Corp. 91

 ROM, PAL and PLA Configurations
Fixed Programmable Programmable
Inputs AND array OR array Outputs
(decoder) Connections

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array

(c) Programmable logic array (PLA) device

92
Read Only Memory
 Read Only Memories (ROM) or Programmable
Read Only Memories (PROM) have:
• N input lines,
• M output lines, and
• 2N decoded minterms.
 Fixed AND array with 2N outputs implementing
all N-literal minterms.
 Programmable OR Array with M outputs lines to
form up to M sum of minterm expressions.

93
Read Only Memory
 A program for a ROM or PROM is simply a
multiple-output truth table
• If a 1 entry, a connection is made to the
corresponding minterm for the corresponding
output
• If a 0, no connection is made
 Can be viewed as a memory with the inputs as
addresses of data (output values), hence ROM or
PROM names!

94
 Read Only Memory Example
 Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output
lines)
 The fixed "AND" array is a
D7 X X X
“decoder” with 3 inputs and 8 D6
outputs implementing minterms. D5 X X
D4 X
 The programmable "OR" A A2 D3
D2 X
array uses a single line to B A1 D1 X X
X
represent all inputs to an C A0 D0

OR gate. An “X” in the

array corresponds to attaching the
minterm to the OR
F0
 Read Example: For input (A2,A1,A0) F3 F2 F1

= 001, output is (F3,F2,F1,F0 ) = 0011.

 What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
95
Programmable Array Logic (PAL)
 The PAL is the opposite of the ROM, having a programmable set
of ANDs combined with fixed ORs.
 Disadvantage
• ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.

 Advantages
• For given internal complexity, a PAL can have larger N and
M
• Some PALs have outputs that can be complemented, adding
POS functions
• No multilevel circuit implementations in ROM (without
external connections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.
96
Programmable Array Logic Example
AND gates inputs

 4-input, 3-output PAL 0 1 2 3 4 5 6 7 8 9

X
Product 1
with fixed, 3-input OR term

2
X X
F1
terms 3

 What are the equations I 1= A

X X
for F1 through F4?
X
4
X X
5 F2
F1 = A B + C X X
6
F2 = A B C + A C + A B
I2 = B
F3 = AD + BD + F1 7
X X

= AD + BD + A B + C 8
X X
F3

F4 = AB + CD + F1 9
X

= AB + CD + (A+B)C I3 = C
X X
= AB+ CD + AC + BC 10
X X
11 F4
X
12
I4 = D
0 1 2 3 4 5 6 7 8 9
97
PAL16H8
http://www.datasheets.org.uk/pdf-datasheets/Databooks-2/Book291-186.html

98
Programmable Logic Array (PLA)
 Compared to a ROM and a PAL, a PLA is the most
flexible having a programmable set of ANDs combined
with a programmable set of ORs.

 Advantages
• A PLA can have large N and M permitting
implementation of equations that are impractical
for a ROM (because of the number of inputs, N,
required 
• A PLA has all of its product terms connectable to
all outputs, overcoming the problem of the limited
inputs to the PAL ORs
• Some PLAs have outputs that can be complemented,
adding POS functions
99
Programmable Logic Array (PLA)
 Disadvantages
• Often, the product term count limits the application
of a PLA.
• Two-level multiple-output optimization is required
to reduce the number of product terms in an
implementation, helping to fit it into a PLA.
• Multi-level circuit capability available in PAL not
available in PLA. PLA requires external
connections to do multi-level circuits.

100
Programmable Logic Array Example
A  What are the equations for F1 and F2?
 F1 = AB +BC + AC
 F2 = (AB + A’B’)’ = (A’ + B’) (A + B) = A’B + AB’
B  Could the PLA implement the
functions without the XOR gates?
No. If only SOP functions used, requires at least 5 AND
C
gates.
X X 1 X X AB

X X 2 X BC X Fuse intact
Fuse blown
X X 3 X AC

X X 4 X AB
X 0
C C B B AA
X 1
 3-input, 3-output PLA F1
with 4 product terms
F2
101
Complex Programmable Logic Devices: CPLD

Complex Programmable Logic Devices (known as CPLDs):

Instead of a single PAL or PLA on a chip, many PALs or
PLAs can be placed on a single CPLD chip and
interconnected.
CPLDs typically contain 500 to 16,000 logic gates.
Each Function Block in a CPLD is a programmable AND-
OR array that is configured as a PLA.

102
 CPLDs - 2
Description of rest of previous figure:

 Each macrocell (MC) contains a flip-flop and MUXs to route

signals from function block to the I/O block or to the
Interconnect Array (IA).
 IA selects signals from the macrocell outputs or I/O blocks
and connects them back to function block inputs
  A signal generated in one function block can be used as an
input to any other function block.
 I/O blocks provide an interface between the bidirectional I/O
pins on the IC and the interior of the CPLD.
FPGAs - Introduction

 ICs that contain an array of identical logic blocks with

programmable interconnections.
 Three major programmable elements in FPGAs: the logic
block, the interconnect (routing), and the input/output block.
 Programmable logic blocks are created by using multiplexers,
look-up tables (LUTs), and AND-OR or NAND-NAND arrays.
 Have revolutionized the way prototyping and designing is done
in the world due to flexibility as it is reprogrammable.
 Vendors: Xilinx, Altera, Lattice Semiconductor, and Microsemi.

104
FPGAs - Layout
FPGAs - Introduction (continued)

 Advantages:
• Reduction in manufacturing time as one adopts
FPGAs instead of MPGAs.
• Easier design iterations.
• Less costly to correct design mistakes or
specification changes.
• Reduced prototyping costs.
• At low volumes, FPGAs are cheaper than MPGAs.

106
 FPGAs - Introduction
(continued)

 Disadvantages:
• Are less dense than traditional gate arrays (MPGAs).
• A lot of resources are needed to achieve programmability.
• MPGAs have better performance than FPGAs.
• Interconnection delays are unpredictable in FPGAs.
• PLDs such as PALs and GALs are simple and inexpensive.
• CPLDs are faster, cheaper and more predictable in timing
than FPGAs.

107
 FPGAs - Organization

 Four different basic architectures or

topologies:
• Matrix-based (symmetrical array)
• Row-based
• Hierarchical PLD
• Sea-of-gates (also called sea of tiles, sea of cells)

108
 FPGAs - Organization
(continued)

 Matrix-based (symmetrical array):

• Manufacturer: Most Xilinx FPGAs are here.
• Large granularity: capable of implementing 4-
variable functions or more.
• Typically contain 8 x 8 arrays in the smaller chips
and 100 x 100 or larger arrays in the bigger chips.
• Routing: two-dimensional channeled (horizontal
and vertical).

Chapter 6 - Part 1 109

FPGAs - Organization
(continued)
 Matrix-based (symmetrical array):

110
 FPGAs - Organization
(continued)

• Row-based:
 Inspired by traditional gate arrays.
 Traditional mask-programmable gate arrays use very similar
architectures.
 Routing: one-dimensional channeled routing, as the routing
resources are located as a channel in between rows of logic
resources.
 Manufacturer: some Microsemi FPGAs employ this
architecture.

111
FPGAs - Organization
(continued)
• Row-based:

112
 FPGAs - Organization
(continued)

 Hierarchical PLD:
• Blocks of logic cells are grouped together by a
local interconnect, and several such groups are
interconnected by another level of interconnect.
• Manufacturer: Altera APEX20 and APEX II.

113
FPGAs - Organization
(continued)
 Hierarchical PLD:

114
FPGAs - Organization
(continued)
 Sea-of-gates:
• Consists of a large number of gates with an
interconnect superimposed on the sea of
gates.
• Manufacturers: Plessey- mid 1990’s (sea-of-
gates), Microsemi Fusion (sea of tiles).

115
FPGAs (continued)
 Sea-of-gates:

116
FPGAs - Programming
Technologies
 Consist of a large number of logic blocks
interspersed with a programmable
interconnect.
 What is programmable:
• The logic block: the same building block can be
“programmed” or “configured” to create any
desired circuitry.
• Interconnections between the logic blocks.
117
FPGAs - Dedicated Specialized Components

 Recently, FPGA vendors have included:

• Dedicated memory
• Dedicated arithmetic units/dedicated multipliers
• DSP processors
• Embedded processors
• Content Addressable Memories (CAM)

118
FPGAs - Applications

 Applications include:
• Rapid prototyping
• FPGAs as Final Product in Medium-Speed
Systems
• Reconfigurable Circuits and Systems
• Glue Logic
• Hardware Accelerators/Coprocessors

119
FPGAs - Example
Summary of Programmable Logic Devices

 Programmable logic comes in different types:

• 1. Devices that can be programmed only once.
 Factory programmable
• Examples: mask-programmable gate array (MPGA) and
read-only memory (ROM).
• 2. Devices that can be reprogrammed many times.
 Field programmable
• Examples: simple programmable logic device (SPLD),
complex programmable logic device (CPLD), and field
programmable gate array (FPGA).

121
Summary of Programmable Logic Devices

122
Summary of Programmable Logic Devices