Digital Logic & Processors

Memory Unit – Flip-flops

 Memory Unit
• The flip-flop is the basic unit of digital memory.

• A flip-flop can store one bit of data.

• Sets of flip-flops are called registers, and can

hold bytes of data.
• Sets of registers are called memories, and can
hold many thousands of bits, or more.

10/30/22
 Sequential Circuits
Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

Types of Triggering
•Level Triggering
•Edge Triggering

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 Latches
SR Latch

S R Q
S Q 0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q 1 1 Q0 No change

 A latch with clock input is known as a flip-flop

A flip-flop is a one bit memory element which can store
either Logic 0 (reset) or Logic 1 (set).
State of a memory element indicates the binary information in the device.
 Latches Vs Flipflops

10/30/22 Source: Confidential 5

 Flip-Flops – SR Flip-flop

Q Characteristic Table

S R Q(t) Q(t+1)
0 0 0 0
Q 0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
S R Q(t+1)
S Q 1 0 1 1
0 0 Q(t)
1 1 0 X
0 1 0
1 1 1 X
1 0 1 R Q
1 1 Invalid Characteristic Equation
Q(t+1) = S+ R’Q
 JK Flip-flop
Characteristic Table

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
J K Q(t+1)
J Q 1 0 1 1
0 0 Q(t)
1 1 0 1
0 1 0
1 1 1 0
1 0 1 K Q
1 1 Q’(t) Characteristic Equation
Q(t+1) = JQ’ + K’Q
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 D Flip-flop

D
D Q D Q(t+1)
0 0
Q 1 1

Characteristic Equation
Characteristic Table
Q(t+1) = D
D Q(t) Q(t+1)
0 0 0
 D flip-flop is known as Data or Delay Flip-flop
0 1 0
 D flip-flops are used in registers to store information
1 0 1
1 1 1
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 T Flip-flop

T J Q T Q T Q(t+1)
0 Q(t)
K Q Q 1 Q’(t)

Characteristic Table
Characteristic Equation
T Q(t) Q(t+1) Q(t+1) = T  Q
0 0 0
0 1 1  T flip-flop is known as Toggle Flip-flop

1 0 1  T flip-flops are used in Counters

1 1 0

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 Flip-Flop Excitation Tables
SR Flip-flop JK Flip-flop
Q(t) Q(t+1) S R Q(t) Q(t+1) J K
0 0 0 X 0 0 0 X
0 1 1 0 0 1 1 X
1 0 0 1 1 0 X 1
1 1 X 0 1 1 X 0

D Flip-flop T Flip-flop
Q(t) Q(t+1) D Q(t) Q(t+1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
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 Flip-Flops with Direct Inputs
• Asynchronous Preset and Clear

Preset

PR PR CLR D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset

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