Unit - 5

Sequential Logic Circuit Design

Introduction

• Every digital system is likely to have combinational circuits, most

systems encountered in practice also include storage elements,
which require that the system be described in term of sequential
logic.
Characteristics of sequential circuit

• Output generation depends upon the previous output and current input signals.
• It depends upon its previous feedback or previous output. It uses the current state (previous
output) as control inputs for the next operations.
• This type of circuit can be two types- Synchronous circuit (uses clock pulse) and Asynchronous
circuit (does not use clock pulse).
• Its basic building block is a flip-flop (binary uit depends upon time instant i.e. depends upon
clock cycles.
• This storage device).
• It has memory elements.
• It is mostly used to build memory devices.
• It is slow in speed.
• Its design and use are complex in comparison with combinational circuits.
Difference between a combinational and a
sequentical logic circuit
combinational logic circuit sequentical logic circuit

Definition At any instant of time, the output is only At any instant of time, the output is determined
dependent on the current state of the inputs. by inputs and the previous outputs.
Time Time is not an important parameter. Time is an important parameter. For timing and
dependency synchronizing of different circuit elements, a
clock signal is necessary.
Memory The output is solely dependent on inputs only. Memory is required to store the previous state of
No need for memory the system.

Design Easy to design and implement with the help of The design of these systems requires basic logic
basic logic gates. gates and flip flops.
Feedback There is no feedback. There is at least one memory element in the
feedback path.
Elementary Its elementary building blocks are logic gates Its elementary building blocks are flip-flops i.e.
building units i.e. AND, OR, NOT, NAND, NOR. memory units.

It is used as a memory device to store data in

Operations It is used for arithmetic and boolean operations.
digital circuits.
Difference between a combinational and a
sequentical logic circuit
combinational logic circuit sequentical logic circuit
Hardware They are easier to implement but They are difficult to implement but
and cost costly, due to hardware. Their less costly than combinational
implementation requires more circuits.
hardware.
Speed They are faster since all inputs are They are slower, because of the
applied at the same time. secondary inputs. So, there is a delay
in between inputs. And the output is
gated by a clock signal.
Block
diagram

Application Half adder, full adder, mux, decoder Flip-flop, counters, registers
Latch

• Latch is the fundamental building block of digital electronics system used

in computers and many other systems. It is the data storage element which
stores 0’s and 1’s.
• It is level sensitive which means when enable is high output is in
accordance to the input. It is sensitive to the pulse duration.
• A basic latch can be made using NOR gates as well as the NAND gates.
• It is just a simple combinational circuit, then what makes it different is
the feedback mechanism which we used.
• They are not useful for synchronous sequential circuits
• They are useful for asynchronous sequential circuits
Different types of latches

• SR Latch
• Gated SR Latch
• D Latch
• Gated D Latch
• JK Latch
• T Latch
SR Latch

• The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND
gates.
• It has two inputs labeled S for set and R for reset.
S  set
R  reset
Q  1, Q '  0  set state
Q  0, Q '  1  reset state
S  1, R  1  undefined, Q and Q' are set to 0
In normal conditions , avoid S  1, R  1
S  set
R  reset
Q  0, Q '  1  set state
Q  1, Q '  0  reset state
S  0, R  0  undefined, Q and Q' are set to 1
In normal conditions , avoid S  0, R  0
Logic diagram using NOR and NAND gate
Modified SR latch using NAND gate

• The SR LATCH using NAND gates can be converted to have the same truth
table as a regular SR LATCH using NOR gates by inverting the inputs.
• Instead of using inverters, we can use NAND gates with common input as
shown in the following figure
State transition table/characteristic table
and state diagram
Gated SR Latch

• The operation of the basic SR latch can be modified by providing an additional control input
that determines when the state of the latch can be changed.
• When the E=0, the outputs of the two AND gates are forced to 0, regardless of the states of
either S or R. Consequently, the circuit behaves as though S and R were both 0, latching the
Q and not-Q outputs in their last states.
SR (Set/Reset) Latch

• SR Latch

• Consider the four

possible cases: R
N1 Q
– S = 1, R = 0
– S = 0, R = 1
– S = 0, R = 0 N2 Q
S
– S = 1, R = 1
SR Latch Analysis

– S = 1, R = 0: 0
R 1
N1 Q
then Q = 1 and Q = 0 0

0
0
1 N2 Q
S

– S = 0, R = 1: R
1
0
N1 Q
then Q = 1 and Q = 0 1

0
1
0 N2 Q
S
SR Latch Analysis

– S = 0, R = 0: Qprev = 0 Qprev = 1

then Q = Qprev R
0
0 R
0
N1 Q N1 Q
– Memory!
0 N2 Q 0 N2 Q
S S

– S = 1, R = 1: R
1
0
N1 Q
then Q = 0, Q = 0 0

– Invalid State 0
0
1 N2 Q
Q ≠ NOT Q S
 SR-Latch
State Equations
Symbol Pre Truth Table

Qn+1 S R Pre Rst Qn 1

S SET
S Q x x 1 0 0
R R x x 0 1 1
CLR
Q 0 0 1 1 Qn
0 1 1 1 0
Rst
1 0 1 1 1
Equation (level clock)
1 1 1 1 x

Qn 1  S RQn  S R
D Latch

• One way to eliminate the undesirable condition of the

indeterminate state in SR latch is to ensure that inputs S and R are
never equal to 1 at the same time. This is done in the D latch.
Gated D Latch
 D-Latch
State Equations
Symbol Pre Truth Table

D SET Qn+1 D E Pre Rst Qn 1

D Q
x x 1 0 0
E E
x x 0 1 1
CLR
Q x 0 1 1 Qn
0 1 1 1 0
Rst
1 1 1 1 1
Equation (level clock)

D = Data Input
Qn 1  EQn  EDn E = Enable Input
Pre = Preset Input
Rst = Reset Input
JK Latch
T Latch
Advantages & Disadvantages of Latches

• Advantages:
• Latch circuits designs are more flexible as compared to flip-flop circuits.
• Digital latches are used in high speed circuit designs as they are faster and it has no need to wait for a clock
input signal due to higher clock speeds as they are asynchronous in design and clock is not used over there.
• They are small and acquire less size of area as latches based circuits have small die size and they are more
successful in high speed circuits designs.
• They consume less power.
• Disadvantages:
• There is a chance to affect the race condition, hence, Latches are less predictable.
• As latches are level sensitive, there are also some chances of meta-stability.
• Application of Latches
• As latch is single bit storage element, they may be used as storage device in power gating circuits and clock
• They may be used as pulse latches where they perform the same behavior like flip-flops by pulsing the clock
very quickly.
• They are widely used in data storage and computing. In short, no latches & Flip-flops, = no digital
electronics and computers.
Flip Flop

• Flip Flop is also the fundamental building block of digital electronics systems. It is the
data storage element which stores 0’s and 1’s. It comprises of the basic unit latch plus
the clock signal which makes a flip flop.
• It is edge triggered i.e. they are sensitive to pulse transitions. The signal only propagates
through it on the rising or falling edge of the clock signal. This is what it makes different
from a latch.
• A basic flip flop is similar to the gated SR latch only the difference is that it does not
have the enable signal instead it has a clock signal which at regular interval of times
changes.
Clock input

• It emits a series of pulses with a precise pulse width and precise

interval between consecutive pulses
• Timing interval between the corresponding edges of two
consecutive pulses is known as the clock cycle time, or period
operation of flip flop

• During the positive or negative edge of the clock signal the change
in the output is taken in accordance to the inputs, hence it is edge
triggered circuit.
• If the transition is at the positive edge of the clock then it is
called positive edge triggered circuit
• if it is at the negative edge of the clock then it is called negative
edge triggered circuit.
• It can be any edge triggered according to the gates and the clock
signal given.
operation of flip flop
Types of Flip Flops

• SR Flip Flop
• D Flip Flop
• JK (Master Slave) Flip Flop
• T Flip Flop
 D-FF Truth Table
Qn follows D on Rising Edge of CLK
Symbol Pre
Truth Table

D Clk Pre Rst Qn 1

D SET Qn+1
D Q
d d 1 0 0
Clk
d d 0 1 1
Q Qn
CLR
d 0 1 1
Rst d 1 1 1 Qn
0  1 1 0

Equation (rising clock)

1  1 1 1

Qn 1  Dn D = Data Input
Clk = Clock input
Qn = Register Output
Logic diagram
Characteristic table

Qn 1  Dn
Characteristic table and Excitation table

Qn 1  Dn
 T-FF (Toggle)
Changes state on every tick of CLK

Symbol
Pre T Clk Pre Rst Qn 1
x x 1 0 0
Qn+1
T T
SET
Q x x 0 1 1
Clk x 0 1 1 Qn
CL Q x 1 1 1 Qn
Qn
R

0  1 1
Rst
1  1 1 Qn
Equation (rising clock)
Truth Table
Qn 1  TQn  T Qn
Logic diagram
Characteristic table
Characteristic table and Excitation table

Qn 1  TQn  T Qn
 SR-FF

Symbol
S R Clk Pre Rst Qn 1
Pre
d d d 1 0 0
S SET Qn+1 d d d 0 1 1
S Q
Clk d d 0 1 1 Qn
R d d 1 1 1 Qn
R Q
Qn
CLR
0 0  1 1
Rst
0 1  1 1 0
1 0  1 1 1
1 1 1 1 ???

Truth Table
Logic diagram using NOR and NAND gate
Characteristic table
Characteristic table and Excitation table

Equation (rising clock)

Qn 1  S RQn  S R
 JK-FF
J K Clk Pre Rst Qn 1
Symbol
d d d 1 0 0
Pre
d d d 0 1 1
d d 0 1 1 Qn Qn+1
J J
SET
Q
d d 1 1 1 Qn Clk
0 0  1 1 Qn K
K CLR
Q
0 1  1 1 0
Rst
1 0  1 1 1
1 1
 1 1 Qn
Equation (rising clock) Truth Table

Qn 1  J Qn  KQn
Logic diagram
Characteristic table and Excitation table
Combined excitation table
 LATCH Vs FLIP-FLOP

S.N
LATCH FLIP-FLOP
o
A Latch is a bistable device, and the state of the latch is represented as 0 Flip-Flop is also a bistable device and there are two stable states of Flip-Flop,
1.
and 1. which are represented as 0 and 1.
2. A Latch is a level triggered device. Flip-flop is an edge triggered device.
3. We cannot classify the Latch. We can classify the flip-flop as synchronous or asynchronous flipflops.

To form sequential circuits, Flip-Flop is constructed from latches along with an

4. To form sequential circuits, latches are constructed from logic gates.
additional clock signal.

5. Latches are fast as compared to the Flip-Flop. Flip-Flops are slow as compared to the latches.
6. Less power is consumed by the Latches. More power is consumed by the Flip-Flop.
7. The latches can or need not have control input. (Gated or non-gated) For all the time, Flip-Flops are clocked.
Only binary inputs can be used to operate the latches when the control
8. Both the clock signal and binary inputs are used to operate the Flip-Flop
signal is HIGH.
The latch is sensitive to the input and as long as it is 'On', we can transmit Flip-Flop is sensitive to the clock signals and until there is a change in the input
9.
the data. clock signal, it never changes the output.

The latch cannot be used as a register because the register requires more
10. Flip-Flop can work as a register because it contains clock signals in its input.
advanced electronic circuits where time plays an essential role.
The latch is asynchronous because latch does not work on the basis of the
11. Flip-Flop is synchronous because flip-flop work on the basis of the clock signal.
clock/time signal.
12. Latches are responsive towards faults on enable pin. Flip-Flops are protected toward fault.
Symbols for latches and flipflops
Applications of flip-flops

• Counters
• Frequency Dividers
• Shift Registers
• Storage Registers
• Bounce elimination switch
• Data storage
• Data transfer
• Latch
• Registers
• Memory
Shift register

• Registers are devices that are meant to store data.

• Each flip-flop can store a single bit of information.
• Cascading n flip-flops, it can store n bits of information – this is called an n-bit register.
• The data stored in the registers can be moved stage-wise within the registers and/or
in/out of the register by applying clock pulses. Such a register is called a shift register.
• Shift registers produce a discrete delay of a digital signal or waveform.
• a four stage shift register delays “data in” by four clocks to “data out”.
• The stages in a shift register are delay stages, typically type D flip flop or type JK flip
flop.
• There are various kinds of shift registers
• depending on the mode of data shift viz.,
• serial-in serial-out register (SISO),
• serial-in parallel-out register (SIPO),
• parallel-in serial-out register (PISO),
• parallel-in parallel-out register (PIPO).
• depending on the direction of data movement they can be either
• left-shift
• right-shift
Shift left register

A Shift Register can shift the bits either to the left or to the right. A Shift Register, which shifts the
bit to the left, is known as "Shift left register", and it shifts the bit to the right, known as "Right left
register".
Shift Right register

A Shift Register can shift the bits either to the left or to the right. A Shift Register, which shifts the
bit to the right, known as " Shift Right register".
serial-in serial-out register (SISO)

• The shift register, which allows serial input (one bit after the other through a single data
line) and produces a serial output is known as Serial-In Serial-Out shift register.
• Since there is only one output, the data leaves the shift register one bit at a time in a
serial pattern
• The logic circuit given below consists of 4 D flip-flops connected in a serial manner.
• All these flip-flops are synchronous with each other since the same clock signal is applied
to each flip flop.
• The main use of a SISO is to act as a delay element.
serial-in serial-out register (SISO) example

• Let us assume data to be ‘1010’.

• Register is initially cleared, forcing all
four outputs to zero and then the input
is applied sequentially to the first flip-
flop on the left (FF0).
• One bit is transmitted from left to right
for every clock pulse which acts as a
common input to all the Flip-Flops.
• Each Flip-Flop can store one bit (either
‘0’ or ‘1’).
• To obtain the data out of the register,
they must be shifted out serially.
• After 4th CLK signal, Data is completely
stored in the Register.
serial-in parallel-out register (SIPO)

• The shift register, which allows serial input (one bit after the other through a single data line) and produces a
parallel output is known as Serial-In Parallel-Out shift register.
• The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four D flip-flops
which are connected.
• The output of the first flip flop is connected to the input of the next flip flop and so on. All these flip-flops are
synchronous with each other since the same clock signal is applied to each flip flop.
• They are used in communication lines where demultiplexing of a data line into several parallel lines is required
because the main use of the SIPO register is to convert serial data into parallel data.
• SIPO is useful for controlling a large number of outputs, including LEDs, whereas, PISO is good for gathering a
large number of inputs, like buttons.
parallel-in serial-out register (PISO)

• The shift register, which allows parallel input (data is given separately to each flip flop and in a simultaneous
manner) and produces a serial output is known as Parallel-In Serial-Out shift register.
• The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists of four D flip-flops
which are connected.
•  All these flip-flops are synchronous with each other since the same clock signal is applied to each flip flop.
• Here the data is to be loaded at the input of each flip-flop. At the same time, while applying the clock pulse, the
data at the output of each flip-flop will be moved to the input of the next flip-flop
• So to avoid conflicts between the loaded data and the shifted data at the inputs, the control input is added in this
shift register.
• A Parallel in Serial out (PISO) shift register is used to convert parallel data to serial data.
parallel-in parallel-out register (PIPO)

• The shift register, which allows parallel input (data is given separately to each flip flop and in a simultaneous
manner) and also produces a parallel output is known as Parallel-In parallel-Out shift register.
• The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists of four D flip-
flops which are connected. 
•  In this type of register, there are no interconnections between the individual flip-flops since no serial shifting
of the data is required. Data is given as input separately for each flip flop and in the same way, output also
collected individually from each flip flop.
• A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like SISO Shift register
it acts as a delay element.
Timing comparison

• n – number of bits in data

• Loading – number of clock pulses
needed to load the data in the
shift register.
• Reading - number of clock pulses
needed for the entire data to
reach the output after loading
the entire data in the register.
• Total= Loading + Reading
Bidirectional Shift Register

• If we shift a binary number to the left by one

position, it is equivalent to multiplying the
number by 2 and if we shift a binary number to
the right by one position, it is equivalent to
dividing the number by 2.To perform these
operations we need a register that can shift
the data in either direction.
• Bidirectional shift registers are the registers
that are capable of shifting the data either
right or left depending on the mode selected.
• If the mode selected is 1(high), the data will
be shifted towards the right direction and if
the mode selected is 0(low), the data will be
shifted towards the left direction.
• The input data is connected at two ends of the
circuit and depending on the mode selected
only one and gate is in the active state.
Counter

• A counter is a device that stores (and sometimes displays) the number of times a particular event or
process has occurred, often in relationship to a clock signal. 
• Counters are used in digital electronics for counting purpose, they can count specific event happening
in the circuit.
• For example, in UP counter a counter increases count for every rising edge of clock.
• Not only counting, a counter can follow the certain sequence based on our design like any random sequence 0,1,3,2… .
• They can also  be designed with the help of flip flops.
• They are used as frequency dividers where the frequency of given pulse waveform is divided.
• Counters are sequential circuit that count the number of pulses can be either in binary code or BCD
form. The main properties of a counter are timing , sequencing , and counting.
• Counter  works in two modes 
• Up counter- This type of counter counts from zero to the maximum number of counts.  
• Down counter- This type of counter counts from the maximum value to zero value.
• Counters are broadly divided into two categories 
• Asynchronous counter
• Synchronous counter
Asynchronous counter

• In asynchronous counter we don’t use universal clock, only first

flip flop is driven by main clock and the clock input of rest of
the following flip flop is driven by output of previous flip flops.
• The diagram shown is of the 2-bit Asynchronous counter in
which we used two T flip-flops. Apart from the T flip flop, we
can also use the JK flip-flop by setting both of the inputs to 1
permanently
• It is evident from timing diagram that Q0 is changing as soon as
the falling edge of clock pulse is encountered, Q1 is changing
when the falling edge of Q0 is encountered(because Q0 is like
the clock pulse for the second flip flop) and so on.
• In this way ripples are generated through Q0,Q1. hence it is
also called RIPPLE counter. 
• A ripple counter is a cascaded arrangement of flip flops where
the output of one flip-flop drives the clock input of the
following flip flop 
Asynchronous counter
Ripple counter

• Ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives the clock
input of the following flip-flop.
• The number of flip flops in the cascaded arrangement depends upon the number of different logic states
that it goes through before it repeats the sequence a  parameter known as the modulus of the counter.
• A n-bit ripple counter can count up to 2 n states.
• It is also known as MOD n counter. It is known as ripple counter because of the way the clock pulse
ripples its way through the flip-flops.
• Some of the features of ripple counter are:
• It is an asynchronous counter.
• Different flip-flops are used with a different clock pulse.
• All the flip-flops are used in toggle mode.
• Only one flip-flop is applied with an external clock pulse and another flip-flop clock is obtained from the output of the
previous flip-flop.
• The flip-flop applied with an external clock pulse act as LSB (Least Significant Bit) in the counting sequence.
synchronous counter

• In the Asynchronous counter, the present

counter's output passes to the input of the next
counter. So, the counters are connected like a
chain.
• The drawback of this system is that it creates the
counting delay, and the propagation delay also
occurs during the counting stage.
The synchronous counter is designed to remove
this drawback.
• In the synchronous counter, the same clock
pulse is passed to the clock input of all the flip
flops.
• the diagram shown is of a 2-bit synchronous
counter in which the inputs of the first flip flop,
i.e., FF-A, are set to 1. So, the first flip flop will
work as a toggle flip-flop. The output of the first
flip flop is passed to both the inputs of the next
JK flip flop.
Modulus Counters

• Modulus Counters, or simply MOD counters, are defined based on the number of states
that the counter will sequence through before returning back to its original value.
• For example, a 2-bit counter that counts from 002 to 112 in binary, that is 0 to 3 in
decimal, has a modulus value of 4 ( 00 → 1 → 10 → 11, and return back to 00 ) so
would therefore be called a modulo-4, or mod-4, counter.
• Note also that it has taken four clock pulses to get from 00 to 11.
• As in this simple example there are only two bits, ( n = 2 ) then the maximum number
of possible output states (maximum modulus) for the counter is: 2n = 22 or 4.
• However, counters can be designed to count to any number of 2n states in their
sequence by cascading together multiple counting stages to produce a single modulus
or MOD-N counter.
• Therefore, a “Mod-N” counter will require “N” number of flip-flops connected together
to count a single data bit while providing 2n different output states, (n is the number of
bits). Note that N is always a whole integer value.
MOD-4 Counter State Diagram
Up/down counter

• Up/Down counter is the combination of

both the counters in which we can
perform up or down counting by
changing the Mode control input. 
• The up/Down counter is also known as
the bidirectional counter which is used
to count in any direction based on the
condition of the input control pin.
• This up/down counter works in two
modes like count-up mode and count-
down mode.
Synchronous Counter Vs Asynchronous
Counter

S.No. Synchronous Counter Asynchronous Counter

1. In the synchronous counter, all flip flops are In Asynchronous counters, different flip flops
triggered with same clock simultaneously. are triggered with different clock, not
simultaneously..
2. In the synchronous counter, the operation is In Asynchronous counter the operation is
faster. slower.
3. Synchronous counter is also known as Parallel Asynchronous counter is also known as Serial
counter. counter.
4. Synchronous counter produces less error than Asynchronous counter produces more errors
asynchronous counter. than a synchronous counter.
5. Design of the Synchronous counter is complex. Design of the Asynchronous counter is simple.

6. Synchronous counters can work with a flexible Asynchronous counters can work with a fixed
number of count sequences. number of count sequences.