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Philip-Power Dissipation in CMOS Circuit
Philip-Power Dissipation in CMOS Circuit
Philip-Power Dissipation in CMOS Circuit
By
Philip Austin M
Types of Power Dissipation in CMOS circuit.
• Power dissipation in CMOS circuits arises from two different
mechanisms:
• static power, which is primarily leakage power and is caused by the
transistor not completely turning off, and
• dynamic power, which is largely the result of switching capacitive
loads between two different voltage states.
When Static Power dissipation occurs?
• Static power dissipation When a CMOS circuit is in an idle state there
is still some static power dissipation–a result of leakage current
through nominally off transistors.
• Both nMOS and pMOS transistors used in CMOS logic gates have finite
reverse leakage and sub-threshold currents.
• This mainly happen due the diffused electron and diffused ions in the
subtract.
Types of Static Power leakage
• 1) Sub Threshold Leakage
• 2) Gate Leakage
• 3) Junction Leakage
1) Sub threshold Leakage
• Sub threshold Leakage current is the current which flow between
drain and Source.
• Vgs = Vg- vs
• When Vgs<Vt (for nMos)
• Vsg = vs - vg
• When Vsg<|vt| (for pMos)
Sub threshold Leakage
• Note:
• Change in the Voltage of the input net may or may not lead to change
in the logic state of output. But in both the cases dynamic power will
be dissipated. i.e i/p =1 then o/p = 0 , otherwise i/p=0 then o/p=1 in
the case of inverter.
Types of Dynamic Power
• 1) Switching Power
• 2) Internal Power
1) Switching Power
• Switch power is the power dissipated while the charging and
discharging the load capacitor at the output of the cell.
Switching Power Equation
• When the input switches from 1 to 0, the Pmos Transistor turns ON
and changes the load to VDD.
• At, that time, the energy delivered by the power supply is:
• E= C VDD^2
• Now the Energy stored in the capacitor, i.e., the energy used to
charge the capacitor.
• Ec = 0.5CL VDD^2
Cont.
• It is to be noted here that only half of the energy is used to charge the
load capacitor and the other half is dissipated as heat in the Pmos
transistor.
• Now, When the input Switches from o to 1, the Pmos transistor turns
OFF and the Nmos transistor turn ON, dis charging the Capacitor.
Switching Power Equation
• Now, if the input Switch”α” times in a cycle and if the input transition
causes output transition as well, we would say that switching activity
factor is”α”.
• Thus, Pswitching = 0.5αCL(VDD^2)F
• Where f=frequency
• CL = Load Capacitance
• Vdd = Supply Voltage
• α = Switching Factor , (i.e) in digital it can be a Clock signal.
2) Internal Power
• Internal Power is any Power which is dissipated within the boundary
of a cell.
Internal Power
Conditions:
• Pmos is “ON” when :
Vss<=Vin<=VDD-VT
• NMOS is “ON” When:
VT<=Vin<= VDD
• Therefore, both Pmos and Nmos are “ON for:
VT<Vin<VDD-VT
CMOS Typical Signal Analysis
Thank you…