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Computer Architecture&O ECEG 3163 02 Computer Evolution Performance
Computer Architecture&O ECEG 3163 02 Computer Evolution Performance
Performance
Computer Architecture
and Organization
(ECEG-3163 )
UG Program
School of Electrical and Computer Engineering
Generations of Computer
· Vacuum tube - 1946-1957
· Transistor - 1958-1964
· Small scale integration - 1965 on
· Up to 100 devices on a chip
· Medium scale integration - to 1971
· 100-3,000 devices on a chip
· Large scale integration - 1971-1977
· 3,000 - 100,000 devices on a chip
· Very large scale integration - 1978 -1991
· 100,000 - 100,000,000 devices on a chip
· Ultra large scale integration – 1991 -
· Over 100,000,000 devices on a chip
· Electronic Numerical
Integrator And Computer
· Eckert and Mauchly
· University of Pennsylvania
· Trajectory tables for weapons
· Started 1943
· Finished 1946
Too late for war effort
· Used until 1955
The IAS computer had a total of 21 instructions, which can be grouped as follows:
· Data transfer: Move data between memory and ALU registers or between two
ALU registers.
· Unconditional branch: Normally, the control unit executes instructions in
sequence from memory. This sequence can be changed by a branch
instruction, which facilitates repetitive operations.
· Conditional branch: The branch can be made dependent on a condition, thus
allowing decision points.
· Arithmetic: Operations performed by the ALU.
· Address modify: Permits addresses to be computed in the ALU and then
inserted into instructions stored in memory. This allows a program considerable
addressing flexibility.
· The use high-level programming languages and software provided the ability to
load programs,(beginning of OSes)
· Data channels:-independent I/O module with its own processor & Instruction
set. -relieves the CPU of a considerable processing burden .
· Multiplexor :- termination point for data channels, the CPU, and memory.
- schedules access to the memory from the CPU and data channels
· NCR & RCA produced small transistor machines
· IBM 7000
· DEC - 1957
· Produced PDP-1
· Raw speed of the microprocessor is not used unless constant work is feed to
the CPU
· Among the techniques used are
· Data flow analysis: The processor analyzes which instructions are dependent
on each other’s results, or data, to create an optimized schedule of
instructions. In fact, instructions are scheduled to be executed when ready,
independent of the original program order. This prevents unnecessary delay.
· Speculative execution: Using branch prediction and data flow analysis, some
processors speculatively execute instructions ahead of their actual appearance
in the program execution, holding the results in temporary locations. This
enables the processor to keep its execution engines as busy as possible by
executing instructions that are likely to be needed.These and other
sophisticated techniques are made necessary by the sheer power
· We can refine this formulation by recognizing that during the execution of an instruction,
part of the work is done by the processor, and part of the time a word is being transferred
to or from memory. In this latter case, the time to transfer depends on the memory cycle
time, which may be greater than the processor cycle time.
· where p is the number of processor cycles needed to decode and execute the
instruction, m is the number of memory references needed, and k is the ratio between
them.
· The five performance factors in the preceding equation (Ic, p, m, k, t) are influenced by
four system attributes: the design of the instruction set (known as instruction set
architecture), compiler technology (how effective the compiler is in producing an efficient
machine language program from a high-level language program), processor
implementation, and cache
· and memory hierarchy.
· Conclusions
· f small, parallel processors has little effect
· N ->∞, speedup bound by 1/(1 – f)
· Diminishing returns for using more processors
Computer Architecture
and Organization
(ECEG-3202 )
UG Program
School of Electrical and Computer Engineering