JTAG DOMAIN SHARE

20-APRIL-2021
LIANJIANG
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OVERVIEW

‒ JTAG introduction
‒ JTAG DV test

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JTAG IEEE 1149.1

1. Test Access Port have 5-wire interface

2. Serial Instruction/Data Port
3. Extensible to include user_defined instructions and data registers.
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TAP CONTROLLER STATE

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SOC15 LIGHTWEIGHT DFT VIEW

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ACRONYM

• MTAP Master TAP, the top level of the JTAG network

• STAC Scalable Test Access and Control
• SIB Segment insertion bit
• SelectWSP select wrapper serial port. STAC’s enable signal, controlled by the
parent controllers SIBs
• SEB SIB Exclusion Bit
• SWB Select WIR Bit

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STAC
Overview

 STAC Scalable Test Access Control Architecture

‒ A common architecture for DFX serial test access and control.
‒ Designed with IEEE 1149.1, IEEE 1500, and IEEE 1687.
‒ STAC provide standard plug-and-play interfaces to the SOC15 Scalable
Control Fabric (SCF) for AMD designed IPs

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STAC 1687 TAP CONTROLLER (STC)

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STAC 1687 NETWORK SIBS

With Query/Update and SEB

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STAC ROUTER
 STAC router is used in SOC15 designs to provide a scalable plug-and-play
solution for the IPs using the SCF.
 STAC router is very similar in design to the STAC, but has fewer standard
instructions, controls only a 1687A port
 required instructions implemented in the STAC Router

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JTAG NETWORK
Master TAP
‒ Jtag1687A SIB (Level 1 STAC router, dfx_dft_t. sipr0)
‒ Level 2 STAC router(sipr00-sipr07) -> tile STACs

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JTAG NETWORK
BC1500 order

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JTAG PIPELINE
Wsi
 Design: Flip flop with bypass Mux Wso
DQ DQ
‒ Insert pipeline registers on the WSO/WSI path between
STAC, Routers and the master TAPs
PipelineEn
 Usage: Wrck

‒ Play the role of repeaters to help with timing.

‒ Enables faster shift clock, but at the cost of more bits to shift.
‒ Enabled by MTAP PIPELINEMODE value, default is disabled.
 Example with 2 WSI and 2 WSO pipeline stages:

Wsi Wsi
R07
Wso Wso Wso
Wsi Wsi
Wso

stac stac

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JTAG PIPELINE
EXAMPLE

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HOW TO ACCESS A TDR
PATTERN GENERATED FROM SG4
1. IEEE1149_1_IR, TOP.IR=8’h13. (P1687A)
2. IEEE1149_1_DR, TOP.1687_SEB/SIB=2’h1; (sib for level1 router).
3. IEEE1149_1_DR, TOP.1687_SEB/SIB=2’h1;TOP.SCF_DFT.STAC_SELWIR=0
STAC_WIR=8’h13; (level1 router’s P1687A).
4. IEEE1149_1_DR, TOP.1687_SEB/SIB=2’h1;TOP.SCF_DFT.STAC_SELWIR=0; TOP.SCF_DFT.R00_SIB
=1; (sib for level2 router).
5. IEEE1149_1_DR, TOP.1687_SEB/SIB=2’h1;TOP.SCF_DFT.STAC_SELWIR=0; TOP.SCF_DFT.R00_SIB
=1; TOP.SCF_DFT.R00.STAC_SELWIR=0, TOP.SCF_DFT.R00.STAC_WIR=8’h13;(level2 router’ P1687A).
5. IEEE1149_1_DR, TOP.1687_SEB/SIB=2’h1;TOP.SCF_DFT.STAC_SELWIR=0; TOP.SCF_DFT.R00_SIB
=1; TOP.SCF_DFT.R00.STAC_SELWIR=0; TOP.SCF_DFT.R00.ACP_SIB=1;(sib for IPs in R00).
6. IEEE1149_1_DR, TOP.1687_SEB/SIB=2’h1;TOP.SCF_DFT.STAC_SELWIR=0; TOP.SCF_DFT.R00_SIB
=1; TOP.SCF_DFT.R00.STAC_SELWIR=0; TOP.SCF_DFT.R00.ACP_SIB=1;SCF_DFT.ACP.STAC_SELWIR=0,
SCF_DFT.ACP.STAC_WIR=3.(select BC1500_en).
7. Configure ACP.BC1500_NETWORK_SIB=1; (enable signals for BC1500 tiles)
8. Configure ACP.WIR to select A TDR. (all BC1500 tiles under the STAC get same WIR. Broadcast)
9. Configure TDR value.
10.Reset network below router1. All sib set 0,all selwir set 1.
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HOW TO ACCESS A TDR

TRACE RTL

 TDR has an enable signal xxTdr_en to gate capture/shift/update signal.

 xxTdr_en is decoded from tile_dfx_xx.bc1500.reg_IR. reg_IR controlled by sel_wir
ir_c/s/u, and its si is wsi_broadcast.
 TDR’s capture/shift/update comes from dr_c/s/u, dr_c/s/u = c/s/u&!sel_wir; Ir_c/s/u
= c/s/u&sel_wir
 sel_wir comes from 1bit TDR JTAG1500BC_SWB.
 JTAG1500BC_SWB SwbEn is a sib (the sib also gate bc1500 c/s/uWR) <- -
Jtag1500bcReg <- - 1500BC TDR <- - BC1500_en is decoded from stac_core.WIR.

 Stac: tile_dfx_xx.xx_stac has an enable signal stac_selectWSP to enable

capture/shift/update in stac_core. IP’s Selectwsp is decoded from 1687 sib of
stac router. Several STAC routers share an upper level stac router. And 1st stac
router controlled by MTAP.

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CCX TDR ACCESS

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STAC HIERARCHY ALTTAP MODE

 The AltTap access mechanism allows embedded 3rd party TAP controllers to be
controlled directly from the TAP pins of the chip
 This mode is used when 3rd party tools (e.g.,DAP,) require the embedded TAP
to be directly accessed from TAP pins
 This access mechanism works hierarchically using instructions in the master TAP
and each of the STCs:
‒ The master TAP ,router and STAC have an ALTAPEN instruction and TDR
‒
 Third party TAP controllers require an AltTdoEn output, to enable the TDO pin
of the SoC for Shift-DR and Shift-IR states.

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SG4
 TDRs defined in SGXML, use Firefox to open.
$STEM/out/linux_2.6.32_64.VCS/arden/common/pub/src/meta/sigdata/sgxml/
arden_A0.sgxml
 Event::IEEE1149_1_IR and Event::IEEE1149_1_DR are used.

 dut[“SCF_DFT.xxx.xxx.xxx.xx_TDR”][“field0”](value0)
[“field1”](value1).write().apply();

dut[“SCF_DFT.xxx.xxx.xx_TDR”].(TDR_value).write().apply();

dut[“SCF_DFT.xxx.xxx.xx_TDR”].set_measure_value(xx_value);
dut[“SCF_DFT.xxx.xxx.xx_TDR”].read().apply();

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CHAIN CHECK
jtag overshift.

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JTAG TEST

 dfx_jtag_simple
Select 1 stac from each level 2 router .write SHIFT_CNT TDR, read and check.
It’s a sqf/autosmoke test to guarantee/monitor jtag design/tb in good condition.

 dfx_jtag_idcode_manid
read and check IDCODE/MANID TDR.
IDCODE need update. http://twiki.amd.com/twiki/bin/view/SIG/IDCODE
MANID no need update, usually read a powerstate.

 dfx_bscan_bsrsegment
use the BSRCONFIG TDR to bypass the bscan chain and verify each sub-chain length.

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JTAG TEST

 dfx_jtag_STAC_*
get stac name from test.dv, write SHIFT_CNT TDR and read back to compare and check
value in RTL. BYP_SCM_SEGMENT/ROS_SETUP access. bc1500 tiles under the stac are also
verified. Designer provide jtag network doc.
GSKT STAC cannot use dfx_jtag_STAC.cpp file. Need additional test cpp file for GSKT.

 dfx_jtag_STAC_*_pipeline
Inherited from dfx_jtag_STAC_*, only difference is PIPELINEMODE=1.
dfxip test dfx_stac_pipeline.cpp can substitute for soc pipeline tests, except gasket stac.
Fail example:
DENAVI24DFX-81
DENAVI24DFX-23

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JTAG TEST

 dfx_overshift_register
This test checks for all the documented Registers inside the SGXML for the following against the below
features against RTL.
a. Opcode decode b. Size of the TDR c. Rest Value of the TDR

In this test a 16bit signature value is appended to the TDR along with the reset shift In value. When the
signature value is shifted out the 16bit value is measured at TDO.
(8'h40 + 16'hDEAD ) --> Shift into TDR - -> Shift out of TDR--> (16'hDEAD + 8’h40)
<RESET_VALUE> + <Overshift Value> <Overshift Value> + <Reset Value>

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JTAG TEST

 dfx_jtag_*_alttap
program ALTTAPEN for STAC, level2 rounter,level 1 router,MTAP,
then use shift_raw_ir/dr to check IDCODE value of alttap.
use DBREQ_L to exit alttap mode and access mtap tdr.
designer provide alttap list.

 dfx_jtag_coolreset
JTAG triggered cool reset and SHIFT_CNT TDR value not be reset.
 dfx_jtag_AVFS_TDR_access*
Write AVFS3_MMSTOP_TOP , read and check.

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[AMD Official Use Only - Internal Distribution Only]

JTAG TEST

 dfx_jtag_ccx_*
Write PWRMON , read and check.

 dfx_tap_smn_access
Basic test to acces the functional register from JTAG -> AXI path.
 dfx_smn_tap_access
access mtap TDR by axi.

 dfx_jtag_umc_multicast
dfx’s rsmu support mult-cast for UMC, config one register for umc0 and check
the result for all umcs
refer to 6.9 of remote_smu_mas_arden.docx Index register support

|26 SOC DFT | <DATE> | CONFIDENTIAL