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A Low Cost FPGA based

Embedded Fingerprint
Verification and Matching
System
2008-MS-E-23
Fahad Naveed Khan
Abstract
Low Cost Fingerprint verification Embedded Platform
Spartan3 FPGA
Leon2 Open core Processor
Verification Algorithm based on NFS2 Open Source Software
Execution time reduction
FPGA based proposed architecture improves substantially the
performance over the baseline system architecture
ntroduction
dentity verification a crucial issue in border and access
control.
Biometrics is a field which uses some unique
physiological and behavioral characteristics, not shared
by any other individual, to positively identify a person.
Physical Characteristics include fingerprints, facial
patterns, hand measurements, eye retinas and irises.
Behavioral characteristics include signature, gait and
typing patterns.
System Architecture
32 bit Sparc Leon 2 Processor
Fingerprint image sensor
Hardware Acceleration and floating point unit
Similar to Thumpod Project in Virtex2 was used
Spartan3 Fpga
FPU (Floating Point Unit)
Software Architecture
NFS Software
Software works with 256 greyscale and 500 ppi scanned images
Linux operating system with a gcc compiler
Minutae extraction algorithm
Low Contrast
Low Ridge FIow
High Curvature
The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. !f the red x still appears, you may have to delete the image and then insert it again.
Minutae extraction
Original image is divided into 8x8 size pixel blocks
For each block a 24x24 sized window is defined
Binary image value extracted from the image
atching AIgorithm
Hardware Architecture
50MHz Leon2 Processor
8kb cache memory
FPU
FPU Performance Benchmark
Execution Times
Conclusion
This paper describes the implementation of a fingerprintminutiae
extraction and matching algorithm running on a Spartan3 based
system with an embedded Leon2 soft-processor.
The original application developed by NST has been modified and
ported to the target platform. Several tests have been carried out to
analyze the performance of the software algorithms with different
Leon2 and GRFPU configurations.
After the insertion of a floating-point unit, the results on execution
time of the algorithm have been reduced in a 94.14% for a 40MHz
and 4KB cache memory configuration.

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