LOW-POWER APPROXIMATE UNSIGNED MULTIPLIERS

WITH CONFIGURABLE ERROR RECOVERY

PRESENTED BY ,
P.Nikitha-197Z1A0489
P.Sathvik-197Z1A0490
R.Sravani-197Z1A0498

GUIDE : Dr . Rajasekhar Turaka

Associate Professor
CONTENTS
• ABSTRACT
• REQUIREMENTS
• INTRODUCTION
• EXISTING WORK
• PROPOSED WORK
ABSTRACT
• Approximate circuits have been considered for applications that can tolerate some loss of
accuracy with improved performance or energy efficiency
• Multipliers are key arithmetic circuits in many of these applications including DSP
• A novel approximate multiplier with a low power consumption and a short critical path is
proposed for high performance DSP applications
• This multipliers uses a newly designed approximate adders that limits its carry propagation
to the nearest neighbours for fast partial product accumulation
• Different levels of accuracy can be achieved by using either OR gates or proposed
approximate adder in a configurable error recovery circuit
• The approximate multipliers using these two error reduction strategies are referred to as
AM1 and AM2respectively.Both AM1 and AM2 have a low mean error distance
REQUIREMENTS
• TOOLS REQUIRED
XILINX VIVADO Simulator

• LANGUAGE USED
Verilog code
INTRODUCTION
• Approximate computing has emerged as a potential solution for the
design of energy-efficient digital systems
• Applications such as multimedia and datamining are inherently error-
tolerant and do not require a perfect accuracy in computation
• The proposed multipliers can be configurable into two designs by
using OR gates and the proposed approximate adders for error
reduction ,referred to as approximate multipliers AM1 and AM2
respectively
• Image sharpening and smoothing are considered as approximate
multiplication-based DSP applications
EXISTING WORK
• Here we have designed an 8 X 8 exact multiplier using AND gates and full adders
• After performing AND operations we will be getting pp0, pp1, pp2, pp3, pp4, pp5,
pp6, pp7 partial products as shown in figure
• These partial product accumulation is done in 3 stages
• In first stage pp0-pp7 are divided into 4 parts as pp0&pp1 ,pp2&pp3,
pp4&pp5 ,pp6&pp7.
• When pp0 and pp1 are given to full adders as inputs it produces O1 as output
similarly O2, O3 and O4 are produced as outputs when pp2&pp3, pp4&pp5 and
pp6&pp7 are given as inputs
• In second stage when O1&O2 and O3&O4 are given to full adders as inputs then
O5 and O6 are produced as outputs
EXISTING WORK

• In third stage when O5 and O6 are

given to full adders as inputs then it
produces O7 as output
• This O7 is our final 16 bit output
Fig: output waveform of 8 X 8 exact multiplier
Fig : output waveforms of 8 X 8 exact multipliers
Fig : Area report of 8 X 8 exact multiplier

Fig : power report of 8 X8 exact

multiplier
PROPOSED WORK
• Here we will be designing approximate multiplier using approximate
adders
• Figure below shows the logic diagram and truth table of approximate
adder

(a)
• The partial products which are generated are fed to approximate adder
which generates two output signals sum and error.
• The error which is generated is known as 1st level error and this error
can be recovered using two error reduction techniques
AM1(approximate multiplier 1) and AM2(approximate adder 2)
• In AM1 we will be using OR gates and in AM2 we will be using OR gates
along with approximate adders
BLOCK DIAGRAM
AM1

• When we are accumulating the generated partial products we

will be using 7 approximate adders so 7 error signals (E1-E7)
will be generated as shown in the figure below
Fig : error generation during partial product accumulation
 • Here we will be applying OR gates to accumulate E1 & E2 , E3 & E4 as
well as E5 & E6 .by doing so 6 error vectors are compressed into 3
vectors
• In the next stage 2 OR gates are used to accumulate the newly
generated 3 error vectors along with E7 which will be producing 2
new error vectors
• The final error vector is generated when the newly generated error
vectors are accumulated using OR gates

AM2
• In this process we will we using OR gates to accumulate E1 & E2
as well as E3 & E4 which generates 2 error vectors
• To accumulate E5 & E6 we will use approximate adders which will
generate a new error vector
Fig : error accumulation tree Fig : error accumulation tree
for AM1 for AM2
• Two error vectors from OR gates ,one error vector from approximate
adder and remaining E7 are accumulated using two approximate
adders
• The final error vector is generated when the two newly generated
error vectors are accumulated using approximate adder
• We use mux (2:1) to select one error reduction technique among AM1
and AM2
• We will get the final multiplier output when we add the sum from
approximate adder and the error vector from the mux
Fig : output of 8X8 approximate multiplier
Fig : area report of 8X8 approximate multiplier

Fig : power report of 8X8 approximate multiplier