Microprocessor without

Interlocked Pipelined Stages

(MIPS)
Introduction
• It is a reduced instruction set computer (RISC) instruction set architecture (ISA).
• MIPS is a load-store architecture, which means that only load and store instructions
can access memory. All other instructions (add, sub, mul, div, and, or, etc.) must get
their operands from registers and store their results in a register.
• The first version of the MIPS architecture was designed by MIPS Computer
Systems for its R2000 microprocessor, the first MIPS implementation. Both MIPS
and the R2000 were introduced together in 1985.
• It contains:
1. Registers
2. Memory
3. Instructions
Registers
• The MIPS processor has 32 general-purpose registers, so it takes 5 bits to specify
which one to use.
• The MIPS processor has one standard register file containing 32 32-bit registers for
use by integer and logic instructions. These registers are called $0 through $31
• The MIPS processor has a separate register file for floating point instructions, which
contains another 32 32-bit registers called $f0 through $f31.
• A few special registers
-PC
-Hi & Lo results of multiplication
-Floating point registers
-Control registers (for errors and status)
MIPS Registers
Memory Organization
• Memory is a large 1-dimension array.
• Each location is one byte (8 bits).
• A memory address indexes into the array.
• For a 32-bit computer there are 2^32 memory locations (4GB).
• For a 64-bit computer there are 2^64 memory locations (16EB).
-64-bit ×86 machines tend to be limited to ~48-bits of address
space, or 4PB.
Memory Organization
MIPS Instructions
• Types of Instructions
1. Data Operations
-Arithmetic
-Logical
2. Data transfer
-Load
-Store
3. Sequencing
-Branch
-Jump
MIPS Instruction (cont.)
See MIPS_Instruction_Set.pdf
Instruction Formats
• There are 3 main instruction formats in MIPS. The fields in each type
are laid out in such a way that the same fields are always in the same
place for each type.