FET devices for Nanocircuits

FD SOI, Fin FET, Multi Gate FETs

 Outline

• Introduction
• MOSFET scaling and its impact
• Material and process approaches and
solutions
• Non-classical CMOS
• Conclusions

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 Introduction
• IC Logic technology: following Moore’s Law by rapidly scaling into deep
submicron regime
– Increased speed and function density
– Lower power dissipation and cost per function
• The scaling results in major MOSFET challenges, including:
– Simultaneously maintaining satisfactory Ion (drive current) and Ileak
– High gate leakage current for very thin gate dielectrics
– Control of short channel effects (SCEs) for very small transistors
– Power dissipation
– Etc.
• Potential solutions & approaches:
– Material and process (front end): high-k gate dielectric, metal gate electrodes,
strained Si, …
– Structural: non-classical CMOS device structures
– Many innovations needed in rapid succession

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 International Technology Roadmap for Semiconductors
(ITRS)
• Industry-wide effort to map IC technology generations
for the next 15 years
– Over 800 experts from around the world
• From companies, consortia, and universities
– For each calendar year
• Projects scaling of technology characteristics and requirements, based on
meeting key Moore’s Law targets
• Assesses key challenges and gaps
• Lists best-known potential solutions
– Projections are based on modeling, surveys, literature,
experts’ technical judgment

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 MOSFET Scaling Approach: 2005 ITRS
• MASTAR computer modeling software is used:
detailed, analytical MOSFET models with key
MOSFET physics included
– Initial choice of scaled MOSFET parameters is made
– Using MASTAR, MOSFET parameters are iteratively
varied to meet ITRS targets for either
• Scaling of transistor speed OR
• Specific (low) levels of leakage current

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 ITRS Drivers for Different Applications
• High-performance chips (MPU, for example)
– Driver: maximize chip speedmaximize transistor
performance (metric: , transistor intrinsic delay [or,
equivalently, 1/)
• Goal of ITRS scaling: 1/ increases at ~ 17% per year, historical rate
– Must maximize Ion
– Consequently, Ileak is relatively high
• Low-power chips (mobile applications)
– Driver: minimize chip power (to conserve battery power)
minimize Ileak
• Goal of ITRS scaling: low levels of Ileak
– Consequently, 1/ is considerably less than for high-performance
logic
• This talk focuses on high-performance
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logic,
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which largely drives the technology
1/ and Isd,leak scaling for High-Performance and Low-Power
Logic. Data from 2003 ITRS.
Isd,leak—High Perf
1/—High Perf

1/—Low Power

Isd,leak—Low Power
17%/yr ave. increase

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 Frequency scaling: Transistor Intrinsic Speed and Chip Clock
Frequency for High-Performance Logic. Data from 2003 ITRS.

Intrinsic, 1/

Chip clock: ITRS projection

Chip Clock: assumption is that

only improvement here is from
transistor speed increase

Conclusion: transistor speed

improvement is a critical enabler of 12/24/22
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chip clock frequency improvement
Potential Problem with Chip Power Dissipation Scaling: High-Performance
Logic, Data from 2003 ITRS
100
Relative Chip Power Dissipation

10
Projected cooling capability Static

Dynamic

1
2003 2005 2007 2009 2011 2013 2015 2017

Calendar Year

Unrealistic assumption, to make a point about Pstatic:

all transistors are high performance, low Vt type
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 Potential Solutions for Power Dissipation Problems, High-
Performance Logic

• Increasingly common approach: multiple transistor

types on a chipmulti-Vt, multi-Tox, etc.
– Only utilize high-performance, high-leakage transistors in
critical paths—lower leakage transistors everywhere else
– Improves flexibility for SOC
• Circuit and architectural techniques: pass gates, power
down circuit blocks, etc.
• Improved heat removal, electro-thermal modeling and
design
• Electrical or dynamically adjustable Vt devices (future
possibility)

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 Difficult Transistor Scaling Issues
• Assumption: highly scaled MOSFETs with the
targeted characteristics can be successfully
designed and fabricated
• However, with scaling, meeting transistor
requirements will require significant technology
innovations
– Issue: High gate leakage  static power dissipation
• Direct tunneling increases rapidly as Tox is reduced
• Potential solution: high-k gate dielectric
– Issue: Polysilicon depletion in gate electrode 
increased effective Tox, reduced Ion
– Issue: Need for enhanced channel mobility
– Etc.

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 High K Gate Dielectric to Reduce Direct Tunneling
Tox SiO2 High-k Material
TK
Electrode Electrode

Si substrate
Si substrate

• Equivalent Oxide Thickness = EOT = Tox = TK * (3.9/K), where 3.9 is relative dielectric
constant of SiO2 and K is relative dielectric constant of high K material
– C = Cox = ox/Tox
– To first order, MOSFET characteristics with high-k are same as for SiO2
• Because TK > Tox, direct tunneling leakage much reduced with high K
– If energy barrier is high enough
• Current leading candidate materials: HfO2 (Keff~15 - 30); HfSiOx (Keff~12 - 16)
– Materials, process, integration issues to solve

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 Difficult Transistor Scaling Issues
• With scaling, meeting transistor requirements
requires significant technology innovations
– Issue: High gate leakage  static power dissipation
• Potential solution: high-k gate dielectric

– Issue: polysilicon depletion in gate electrode  increased

effective Tox, reduced Ion
• Potential solution: metal gate electrodes
– Issue: Need for enhanced channel mobility
– Etc.

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Because of the combination of a high-k dielectric and the metal
gate electrode, Intel is quoting a greater than 20% improvement in
switching speed compared to its 65nm transistors. At the same
speed as its 65nm transistors, there's a greater than 5x reduction
in source-drain leakage power and a greater than 10x reduction in
gate oxide leakage power;
 Metal Gate Electrodes
• Metal gate electrodes are a potential solution when
poly “runs out of steam”: probably implemented in
2008 or beyond
– No depletion, very low resistance gate, no boron
penetration, compatibility with high-k
– Issues
• Different work functions needed for PMOS and NMOS==>2 different
metals may be needed
– Process complexity, process integration problems, cost
• Etching of metal electrodes
• New materials: major challenge

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 Limits of Scaling Planar, Bulk MOSFETs
• 65 nm tech. generation (2007, Lg = 25nm) and
beyond: increased difficulty in meeting all device
requirements with classical planar, bulk CMOS
(even with high-k, metal electrodes, strained Si…)
– Control of SCE
– Impact of quantum effects and statistical variation
– Impact of high substrate doping
– Control of series S/D resistance (Rseries,s/d)
– Others

• Alternative device structures (non-classical

CMOS) may be utilized
– Ultra thin body, fully depleted: single-gate SOI
and multiple-gate transistors
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Benefits of SOI technology relative to
conventional silicon (bulk CMOS)
processing include:

1.Lower parasitic capacitance due to isolation

from the bulk silicon, which improves power
consumption at matched performance.
2.Higher performance at equivalent VDD. Can
work at low VDD's.
3.Reduced temperature dependency due to
no doping.
4.Better yield due to high density, better wafer
utilization.
5.Lower leakage currents due to isolation thus
higher power efficiency.
6.Inherently radiation hardened ( resistant to
soft errors ), thus reducing the need for
redundancy.
7.Higher mobility
 Transistor Structures: Planar Bulk & Fully Depleted SOI
Planar Bulk Fully Depleted
SOI

G G
D S
D S BOX

Depletion Region

Substrate Substrate

+ Wafer cost / availability + Lower junction cap

+ Light doping possible
- SCE scaling difficult + Vt can be set by WF of
- High doping effects and Metal Gate Electrode
- SCE scaling difficult
Statistical variation - Sensitivity to Si
- Parasitic junction thickness (very thin)
capacitance - Wafer cost/availability
REFERNCES
1. P.M. Zeitzoff, J.A. Hutchby and H.R. Huff, MOSFET and Front-End Process Integration: Scaling
Trends, Challenges, and Potential Solutions Through The End of The Roadmap, International Journal of
High-Speed Electronics and Systems, 12, 267-293 (2002). 12/24/22
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2. Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001.
 Double Gate Transistor Structure
REFERENCES
1. P.M. Zeitzoff, J.A. Hutchby and H.R. Huff, MOSFET and Front-End
Process Integration: Scaling Trends, Challenges, and Potential
Solutions Through The End of The Roadmap, International Journal of
High-Speed Electronics and Systems, 12, 267-293 (2002).
2. Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001.

Double-Gate SOI:
+ Enhanced scalability
Top
+ Lower junction capacitance
S D
+ Light doping possible
Bottom + Vt can be set by WF of
BOX metal gate electrode
Ultra-
thin FD + ~2x drive current
SUBSTRATE
- ~2x gate capacitance
- High Rseries,s/draised S/D
- Complex process
Summary: more advanced, optimal
device structure, but difficult to
fabricate, particularly in this SOI
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 Field Lines for Single and Double-Gate MOSFETs

To reduce SCE’s,
E-Field lines Double gates
electrically shield
aggressively reduce the channel
Si layer thickness

G G

S D S D

BOX BOX G

Regular SOI MOSFET

Single-Gate SOI Double-gate MOSFET
Double-Gate
Courtesy: Prof. J-P Colinge, UC-Davis
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FinFET Device

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Other Double-Gate Transistor Structures (FinFET)
Gate Gate overlaps fin here
SiO2
Perspective
view of FinFET.
Fin is colored
SiO222 SiO222 yellow.
Source Drain
BOX
Substrate Silicon Courtesy: T-J. King and
C. Hu, UC-Berkeley

Key advantage: relatively Fin

conventional processing,
largely compatible with Top View of
current techniquescurrent FinFET
leading approach
Arrow indicates
Fin Current flow

Source Drain

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Poly Gate 23
FinFET disadvantage

Although FinFETs are wonderful from some points of view

(low leakage, high current, lower voltage) they have some
disadvantages too (higher parasitic capacitance, higher
parasitic resistance due to local interconnect, quantized
device widths). The biggest challenge has probably been
RC extraction accuracy.

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 Types of Multiple-Gate Devices

G G G
D D D

S S S
Courtesy:
Prof. J-P
Colinge, 1 2 3
UC-Davis Buried Oxide

G G
D D
Increasing
1: Single gate
process 2: Double gate S S
complexity, 3: Triple gate
increasing 4: Quadruple gate (GAA) 4 5
scalability
5:gate Buried Oxide

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 Nanowire Transistors

Gate-All-Around Transistors: In a new design, the transistor channel is made

up of an array of vertical nanowires. The gate surrounds all the nanowires,
which improves its ability to control the flow of current. Platinum-based source
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and drain contacts sit at the top and bottom of the nanowires. 26
 Timeline of Projected Key Technology Innovations

2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018

Strained Si--HP Production

High-k (Low Power) Production

Elevated S/D Production

High-k (HP) Production

Metal Gate (HP, dual gate) Production

Metal Gate (Low Power, dual gate) Production

Ultra-thin Body (UTB) SOI, single gate (HP) Production

Metal gate (near midgap for UTBSOI) Production

Strained Si (Low Power) Production

Multiple Gate (HP) Production

Ultra-thin Body (UTB) SOI, single gate (Low power) Production

Multiple Gate (Low Power) Production

Quasi-ballistic transport (HP) Production

Quasi-ballistic transport (LOP) Production

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 Conclusions
• Rapid transistor scaling is projected to continue through the end of the
Roadmap in 2020
– Transistor performance will improve rapidly, but leakage & SCEs will be difficult to
control
• Transistor performance improvement is a key enabler of chip speed
improvement
– Many technology innovations will be needed in a relatively short time to enable this
rapid scaling
• Material and process innovations include high-k gate dielectric,
metal gate electrodes, and enhanced mobility through strained
silicon
– High-k and metal gate electrode needed in 2008
• Structural potential solutions: non-classical CMOS
• Non-classical CMOS and process and material innovations will likely be
combined in the ultimate, end-of-Roadmap device
– Well under 10nm MOSFETs expected by the end of the Roadmap
• Power dissipation, especially static, is a growing problem with scaling:
integrated, innovative approaches
needed
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