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Intro To 8085
Intro To 8085
Intro To 8085
8085 Specifications
Introduced March 1976
0.37 MIPS
Also was used as a computer peripheral controller – modems, hard disks, printers,
8085 Pins
For complete understanding of the interfacing circuits of
memory, I/O devices etc. to the 8085 CPU it is required to learn
about the functions of all the pins of 8085.
The pins of 8085 are classified in following groups:
Address and Data pins
Control & status pins
Interrupt pins
Serial I/O pins
Clock pins
Reset pins
DMA pins
Power supply pins
8085 Architecture
8085 Registers
ALU
Programming examples
8085 Pin configuration
40 pin device
8085 Bus Architecture
8085 Pin Description
Higher Order Address pins- A15 – A8
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
8085 Pin Description
Control Pins – RD, WR
These are active low Read & Write pins
RD – used to control READ operation of the microprocessor
When this pin goes low, the microprocessor reads the data from
memory or I/O device
WR – controls the write operations of the microprocessor
When this pin goes low, data is written to memory or I/O device
8085 Pin Description
IO/M – Used to select I/O or Memory operation
When the pin goes high, the address is for an I/O device.
When the pin goes low, the address is assigned for memory
8085 Pin Description
Interrupt Pins
TRAP,
RST7.5,
RST 6.5,
RST 5.5,
INTR,
INTA
Suppose ADC is using address and data bus, and if LCD requests
use of address and data bus by giving HOLD signal
Z (zero flag),
CY (carry flag)
Flag Register
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY
Flag Register
Sign Flag
Carry Flag
Parity Flag
The memory this register points to is a special area called the stack.
The stack is an area of memory used to hold data that will be retrieved
soon.
Transferring data
3. Control Bus
Synchronization signals
Timing signals
Control signal
8085 Address and Data Buses
The address bus has 8 signal lines A8 –A15 which are unidirectional.
The other 8 address bits are multiplexed(time shared) with the 8 data bits.
During the execution of the instruction, these lines carry the address bits
during the early part, then during the late parts of the execution, they
carry the 8 data bits.
In order to separate the address from the data, we can use a latch to save
the value before the function of the bits changes.
8085 Address and Data Buses
Thus, AD7–AD0 lines are serving a dual purpose and they need to be
demultiplexed to get all the information.
The high order bits of the address remain on the bus for three clock periods.
However, the low order bits remain for only one clock period and they would be
lost if they are not saved externally.
Also, notice that the low order bits of the address disappear when they are
needed most.
To make sure we have the entire address for the full three clock cycles, we will
use an external latch to save the value of AD7–AD0 when it is carrying the
address bits.
Then when ALE goes low, the address is saved and the AD7–
AD0 lines can be used for their purpose as the bi-directional
data lines.
8085 Address and Data Buses
The high order address is placed on the address bus and hold for
3 clk periods,
The low order address is lost after the first clk period, this address
needs to be hold however we need to use latch
The ALE signal is connected to the enable (G) pin of the latch
and the OC –Output control –of the latch is grounded.
8085 Address and Data Buses
Assignment 1