Digital Electronics Chapter 7

Chapter 7
Latches, Flip-Flops and

Timers
Dr Abdelaziz Yousif
Ahmed 22-03-23
Ext: 7845
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Course Outcome
1. Explain number systems, codes, digital arithmetic operation
and circuits.
2. Use Boolean algebra and Karnaugh Maps to minimize
Boolean expressions for the design of digital logic circuits.
3. Explain and use flip-flops, latches, counters, multiplexers and
de-multiplexers.
4. Design and construct combinational digital logic
circuits using appropriate logic design techniques.
5. Design and construct synchronous sequential digital
logic circuits using appropriate logic design techniques.
Learning Outcome
1. Use logic gates to construct basic latches
2. Explain the difference between an S-R latch and a D latch
3. Recognize the difference between a latch and a flip-flop
4. Explain how D and J-K flip-flops differ
5. Understand the significance of propagation delays, set-up time and hold
time in the application of flip-flops
6. Apply flip-flops in basic applications
Outline
1. Latches
2. Flip-Flops
3. Flip-Flop Operating Characteristics
4. Flip-Flop Applications
5. One-Shots
6. The Astable Multivibrator
Sequential Circuits
Introduction to Sequential Circuits
 In Combinational circuit the present output depends on the

present input.

A  1 0
In Out 1 1
B
Cout 0 1
1 0
Combinational Circuit
Sequential Circuits
Difference Between Combinational and Sequential Circuits
In
Out
Memory
Sequential Circuit
The present output depends on the present input
as well as past output.
Latches
The basic storage element is called latch. The latch has two
stable states 0 or 1.
The S-R (Set-Reset) latch is the most basic type. It can be constructed from
NOR gates or NAND gates. With NOR gates, the latch responds to active-
HIGH inputs; with NAND gates, it responds to active-LOW inputs.
NOR Active-HIGH Latch NAND Active-LOW Latch
NAND Active-LOW Latch
NAND Active-LOW Latch

__
Negative-OR equivalent of the NAND gate S-
R latch.
NOR Active-High Latch
NOR gate truth table

A B X
0 0 1
0 1 0
1 0 0
NOR Active-HIGH Latch 1 1 0
Case I: Case II:

R= 1 & S = 0 R= 0 & S = 1
Q= 0 Q= 1 Q=1 Q= 0
R= 0 & S = 0 R= 0 & S = 0
Q=0 Q= 1 Q=1 Q=
Case III:
0
R= 1 & S = 1
Q= 0 Q=
Thomas L. Floyd 0 All Rights Reserved
Truth table for NOR and NAND Latch
Truth table for NOR active-HIGH Latch
Truth table for NAND active-LOW Latch
Latches
If the S-R waveforms below are applied to the inputs of an active-

LOW latch, determine the waveform that will be observed on the
Q output. Assume that Q is initially LOW.
Gated S-R Latch
A gated latch is a variation on the basic
latch.
The gated latch has an additional input,
called enable (EN) that must be HIGH in
order for the latch to respond to the S and R
inputs.
Gated S-R Latch truth table
Gated S-R Latch
Show the Q output with relation to the input signals. Assume Q starts
LOW.
Keep in mind that S and R are only active when EN is

HIGH.
EN
Q
Gated S-R Latch
Determine the Q output waveform with relation to the input signals.

Assume
Q starts LOW (Reset).
Gated D Latch
D
A simple rule for the D latch is:

Q follows D when the Enable is active.
Truth table for the D latch
The truth table for the D latch summarizes its operation. If

EN is LOW, then there is no change in the output and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
Gated D Latch
D Q
EN
Determine the Q output for the
Q
D latch, given the inputs shown.
EN
Q
Notice that the Enable is not active during these times,
so the output is latched.
Gated D Latch
Determine the Q output waveform if the inputs shown in

Figure below are applied to a gated D latch, which is
initially RESET.
Flip-Flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q
D
Q
C C
Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
S-R Flip-flop
S-R flip flop
Truth table for a positive-edge triggered S-R flip flop
D Flip-flop
D
Inputs Outputs Inputs Outputs
D CLK
Q Q Comments D CLK
Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET
(a) Positive-edge triggered (b) Negative-edge triggered
D Flip-flop
Determine the Q and Q output waveform of the
flip-flop for the D and CLK inputs. Assume that
the positive edge-triggered flip-flop is initially
RESET.
J-K Flip-flop
The J-K flip-flop is more versatile than the D flip flop. In addition to
the clock input, it has two inputs, labeled J and K. When both J and
K = 1, the output changes states (toggles) on the active clock edge
(in this case, the rising edge).
J-K Flip-flop
NAND gate truth table
1 J A B X
Q 1010
0 0 1
CLK
1
1 0 Q 0101 0 1 1
1 K
1 0 1
1 1 0
J-K Flip-flop truth table
Inputs Outputs
J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Toggle
Q0 Q0
J-K Flip-flop
J Q
Determine the Q output for the J-K flip-flop, CLK

given the inputs shown.
K
Q
Notice that the outputs change on the leading edge of the

clock.
Set Toggle Set Latch
CLK
J-K Flip-flop
Determine the Q and output waveform of the flip-

flop for the J-K and CLK inputs as indicated.
Assume that the flip-flop is initially RESET.
D Flip-flop
A D-flip-flop does not have a toggle mode like the J-K flip-flop, but
you can hardwire a toggle mode by connecting Q back to D as shown.
This is useful in some counters as you will see in Chapter 8.
D Q
For example, if Q is LOW, Q is CLK CLK

HIGH and the flip-flop will toggle
on the next clock edge. Because Q
the flip-flop only changes on the
active edge, the output will only
change once for each clock pulse. D flip-flop hardwired for
a toggle mode
Asynchronous Preset and Clear Inputs
Synchronous inputs are transferred in the triggering edge
of the clock (for example the D or J-K inputs). Most
flip- flops have other inputs that are asynchronous,
meaning they affect the output independent of the clock.
PRE
Two such inputs are normally labeled
preset (PRE) and clear (CLR). These Q
J
inputs are usually active LOW. A J-
K flip flop with active LOW preset CLK
and CLR is shown.
Q
K
CLR
PRE
Q
Determine the Q output for the J-K J
flip-flop, given the inputs shown.

CLK
Q
K
CLR
Set Toggle Set Reset Toggle Latch
CLK
K Set
PRE Reset
CLR
Q
For the positive edge-triggered D flip-flop with preset and

cleat inputs, determine the Q output for the inputs shown
in timing diagram below if Q is initially LOW.
Flip-Flops Operating Characteristics
Propagation Delay Time
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering

edge
CLK 50% point

CLK
Q 50% point on LOW-to- Q 50% point on HIGH-

HIGH transition of Q
to-
LOW transition of Q
tPLH
tPHL
The typical propagation delay time for the 74AHC family (CMOS) is 4 ns.
Even faster logic is available for specialized applications.
Propagation Delay Time
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.
PRE 50% point CLR 50% point
Q 50% point
Q 50%
point
tPLH
tPHL
Set-up Time and Hold Time
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts
D
Hold time is the minimum time
for the data to remain after the CLK
clock.
Hold time, tH
Flip-Flops Applications
Output
lines
Principal flip-flop applications are
Q0
temporary data storage, for
D
dividers, as and in (which

frequency R
covered in counters
detail in Chapter 9). are D Q1
C
Q2
Typically, for data storage applications, D
a group of flip-flops are connected to Parallel data

C
parallel data lines and clocked together. input lines R
Data is stored until the next clock pulse. D Q3

Clock C
R
Clear
For frequency division, it is simple to use a flip-flop in
the toggle mode or to chain a series of toggle flip flops to
continue to divide by two.
HIGH
HIGH
One flip-flop will divide fin
J QA J QB
by 2, two flip-flops will fout
divide fin by 4 (and so on). A CLK CLK
fin
side benefit of frequency
division is that the output K K
has an exact 50% duty cycle.
fin
Waveforms:
fout
Determine the output fout waveform for the circuit in Figure

below when an 8 kHz square wave input is applied to the
clock input of flip-flop A.
Determine the output waveforms in relation to the clock for QA,

QB, and QC in the circuit of Figure below and show the binary
sequence represented by these waveforms.
One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to
its unstable state for a predetermined length of time,
then returns to its stable state.
+V
REXT CEXT
For most one-shots, the length of time Q
CX
in the unstable state (tW) is RX/CX
Trigger
determined by an external RC circuit.
Q
Trigger
Q
tW
One-Shots
Nonretriggerable one-shots do not respond to any

triggers that occur during the unstable state.
Retriggerable one-shots respond to any trigger, even if

it occurs in the unstable state. If it occurs during the
unstable state, the state is extended by an amount
equal to the pulse width.
Retriggerable one-shot:
Trigger
Retriggers
Q
tW
One-Shots
An application for a retriggerable one-shot is a power
failure detection circuit. Triggers are derived from the
ac power source, and continue to retrigger the one
shot. In the event of a power failure, the one-shot is
not triggered and an alarm can be initiated.
Trigger Missing trigger

s due to power
from ac
derived failure
Q Retriggers Retriggers Power failure indication

tW
tW
tW
The 555 timer as a One-Shot
The 555 timer can be in various ways,

configuredas a one-shot. A basic one shot is shown below.
including
The pulse width is determined by R1C1 and
approximately
is tW = 1.1R1C1. +V CC
(4) (8)
R1
(7) RESET
VCC
(6) DISCH (3)

The trigger is a THRES OUT
negative- (2) (5) tW = 1.1R1C1
TRIG
going pulse.
CONT GND
C1 (1)
The 555 timer
Determine the pulse width for the circuit shown below.
tW = 1.1R1C1 = 1.1(10 k)(2.2 F) = 24.2 ms

+VCC
+15 V
(4)
R1 (8)
10 k (7) RESET
VCC
(6) DISCH (3)

THRES OUT
(2) (5) tW = 1.1R1C1
TRIG
C1 CONT GND
(1)
2.2 F
The Astable Multivibrator
 A 555 timer connected to operate as an astable multivibrator.
 The threshold input (THRESH) is now connected to the trigger input
(TRIG).
 The external components R1, R2, and C1 form the timing network that
sets the frequency of oscillation.
 The 0.01 µF capacitor, C2, connected to the control (CONT) input is
strictly for decoupling and has no effect on the operation; in some cases
it can be left off.
The 555 timer connected as an astable multivibrator (oscillator).

Flip-Flops
Applications
The 555 timer
The 555 can be configured as a basic astable multivibrator with
the circuit shown. In this circuit C1 charges through R1 and R2 and
discharges through only R2. The output frequency is given by:
+VCC
The frequency and duty
cycle are set by these
(4)
components. 1.44 R1 (8)
f  RESET
(7) VCC
 R1  2R2 C 1 (6) DISCH (3)

R2 THRES OUT
(2) (5)
 TRIG
Duty cycle   R1  R2  100%
C1
CONT GND
(1)
  R1  2R2 
Duty cycle   R1  100% 50% duty cycle
 R1  R2 
The 555 timer - Example
A 555 timer configured to run in the astable mode (pulse oscillator).
Determine the frequency of the output and the duty cycle.
1.44
f 
 R1  2R2 C1
= 5.64 kHz
= 59.5 %
Quiz
1. The output of a D latch will not change if

a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above
Quiz
2. The D flip-flop shown will

Q
a. set on the next clock pulse D
CLK CLK
b. reset on the next clock pulse
c. latch on the next clock pulse Q
d. toggle on the next clock pulse
Quiz
3. For the J-K flip-flop shown, the number of inputs that

are asynchronous is
PRE
a. 1
b. 2 J
Q
c. 3 CLK
d. 4 K
Q
CLR
Quiz
4.Assume the output is initially HIGH on a leading edge

triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
CLK
b. 2 J
c. 3 K
d. 4 1 2 3 4
Quiz
5. The time interval illustrated is called

a. tPHL 50% point on triggering
edge
b. tPLH CLK
c. set-up time
Q 50% point on LOW-to-
d. hold time HIGH transition of Q
?
Quiz
6. The time interval illustrated is called

a. tPHL
b. tPLH D
c. set-up time CLK
d. hold time ?
Quiz
7. The application illustrated is a

a. astable multivibrator HIGH HIGH
b. data storage device fout

J QA J QB
c. frequency multiplier
fin CLK CLK
d. frequency divider
K K
Quiz
Output
lines
Q0
8. The application illustrated is a
D
a. astable multivibrator R
D Q1
b. data storage device C
c. frequency multiplier D Q2
d. frequency divider Parallel data

C
input lines R
D Q3
Clock C
R
Clear
Quiz
9.A retriggerable one-shot with an active HIGH output has

a pulse width of 20 ms and is triggered from a 60 Hz line.
The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH
Quiz
10. The circuit illustrated is a +VCC
a. astable multivibrator
(4) (8)
R1
b. monostable multivibrator (7)
RESET
VCC
c. frequency multiplier R2 (6) DISCH

THRES OUT
(3)
(2) (5)
d. frequency divider C1
TRIG
CONT GND
(1)
Quiz
Answers:
1. b 6. d
2. d 7. d
3. b 8. b
4. c 9. d
5. b 10.
a

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Chapter 7

Latches, Flip-Flops and

 In Combinational circuit the present output depends on the

NOR Active-HIGH Latch NAND Active-LOW Latch

NAND Active-LOW Latch

NOR gate truth table

Case I: Case II:

Truth table for NAND active-LOW Latch

If the S-R waveforms below are applied to the inputs of an active-

Keep in mind that S and R are only active when EN is

Determine the Q output waveform with relation to the input signals.

A simple rule for the D latch is:

The truth table for the D latch summarizes its operation. If

Determine the Q output waveform if the inputs shown in

S-R flip flop

Truth table for a positive-edge triggered S-R flip flop

Inputs Outputs Inputs Outputs

(a) Positive-edge triggered (b) Negative-edge triggered

Determine the Q output for the J-K flip-flop, CLK

Notice that the outputs change on the leading edge of the

Set Toggle Set Latch

Determine the Q and output waveform of the flip-

For example, if Q is LOW, Q is CLK CLK

flip-flop, given the inputs shown.

For the positive edge-triggered D flip-flop with preset and

50% point on triggering

CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-

PRE 50% point CLR 50% point

dividers, as and in (which

a group of flip-flops are connected to Parallel data

parallel data lines and clocked together. input lines R

Data is stored until the next clock pulse. D Q3

Determine the output fout waveform for the circuit in Figure

Determine the output waveforms in relation to the clock for QA,

Nonretriggerable one-shots do not respond to any

Retriggerable one-shots respond to any trigger, even if

Trigger Missing trigger

Q Retriggers Retriggers Power failure indication

The 555 timer can be in various ways,

(6) DISCH (3)

Determine the pulse width for the circuit shown below.

tW = 1.1R1C1 = 1.1(10 k)(2.2 F) = 24.2 ms

(6) DISCH (3)

The 555 timer connected as an astable multivibrator (oscillator).

 R1  2R2 C 1 (6) DISCH (3)

1. The output of a D latch will not change if

2. The D flip-flop shown will

d. toggle on the next clock pulse

3. For the J-K flip-flop shown, the number of inputs that

4.Assume the output is initially HIGH on a leading edge

5. The time interval illustrated is called

6. The time interval illustrated is called

c. set-up time CLK

7. The application illustrated is a

b. data storage device fout

d. frequency divider Parallel data

9.A retriggerable one-shot with an active HIGH output has

10. The circuit illustrated is a +VCC