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  • Transition Fault Simulation

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    jiaping tang
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    This document discusses three types of speed failures in integrated circuits: transition faults which model excessive delays at nodes preventing transitions from reaching outputs within clock periods, path delay faults which consider cumulative gate delays along paths causing failures, and segment delay faults which target delays along path segments instead of whole paths. It also notes that transition faults have two possibilities at each line - slow to rise and slow to fall, and test patterns for transition faults consist of initial and test vectors to set the target node value and launch and propagate the desired transition.

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    This document discusses three types of speed failures in integrated circuits: transition faults which model excessive delays at nodes preventing transitions from reaching outputs within clock periods, path delay faults which consider cumulative gate delays along paths causing failures, and segment delay faults which target delays along path segments instead of whole paths. It also notes that transition faults have two possibilities at each line - slow to rise and slow to fall, and test patterns for transition faults consist of initial and test vectors to set the target node value and launch and propagate the desired transition.

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    19 views2 pages

    Transition Fault Simulation

    Uploaded by

    jiaping tang
    This document discusses three types of speed failures in integrated circuits: transition faults which model excessive delays at nodes preventing transitions from reaching outputs within clock periods, path delay faults which consider cumulative gate delays along paths causing failures, and segment delay faults which target delays along path segments instead of whole paths. It also notes that transition faults have two possibilities at each line - slow to rise and slow to fall, and test patterns for transition faults consist of initial and test vectors to set the target node value and launch and propagate the desired transition.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
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    Fault model for speed failures

     Transition fault
    A transition fault at node X assumes a large delay at X such that the transition at X will not
    reach the latch or primary output within the clock period.
     Path delay fault
    The path delay fault model considers the cumulative effect of gate delays along a specific path,
    then the chip fails.
     Segment delay fault
    Segment delay fault targets path segments instead of complete path.
    Transition fault
    At each line in the circuit, two transition faults are possible: slow-to-rise and slow-to-fall.
    Test pattern for a transition fault consists of a pair of vectors{v1,v2}, where v1 （ initial vector ） is
    required to set the target node to an initial value, and v2 （ test vector ） is required to launch the
    appropriate transition at the target node and also propagate the fault effect to a primary output.

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