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Lecture9 MOS Transistor Dynamics
Lecture9 MOS Transistor Dynamics
MOS Transistor
Dynamics
Transistor capacitances
Sub-Micron MOS Transistor
» Threshold Variations
» Velocity Saturation
» Sub-Threshold Conduction and Leakage
Latchup
Process Variations
Future Perspectives
EE415 VLSI Design
Dynamic Behavior of MOS Transistor
Gate Capacitance
Cox ox / tox
Gate Oxide
Gate
Polysilicon Field-Oxide
Source Drain
(SiO2)
n+ n+
G
CGS = Cgs+ CgsO
CGS CGD
CGD = Cgd+ CgdO
S D
CGB = Cgb
CSB CGB CDB
CSB = CSdiff
B
CDB = CDdiff
EE415 VLSI Design
Transistor Capacitance Values
for 0.25
Example: For an NMOS with L = 0.24 m,
W = 0.36 m, LD = LS = 0.625 m CGSO = CGDO = Cox xd W = Co W = 0.11 fF
CG4
M2 M4
CGD12 CDB2 Vout
pdrain Vout2
Vin
ndrain
Cw
CDB1
M1 M3
CG3
high-to-low low-to-high
Keqbp Keqsw Keqbp Keqsw
NMOS 0.57 0.61 0.79 0.81
PMOS 0.79 0.86 0.59 0.7
EE415 VLSI Design
Extrinsic (Fan-Out)
Capacitance
The extrinsic, or fan-out, capacitance is the total gate
capacitance of the loading gates M3 and M4.
Cfan-out = Cgate (NMOS) + Cgate (PMOS)
= (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox)
1.2m
=2
Out
In
Metal1
Polysilicon
0.125 0.5
NMOS
0.375/0.25 GND
Secondary Effects:
•Threshold Variations
•Parasitic Resistances
•Velocity Saturation
•Mobility Degradation
•Sub-threshold Conduction
L VDS
Threshold as a function of Drain-induced barrier lowering
the length (for low VDS) lowers VT for short channel device
EE415 VLSI Design
Variations in I-V Characteristics
sat = 105
Constant velocity
c = 1.5 (V/µm)
EE415 VLSI Design
Velocity Saturation
We assumed carrier velocity is proportional to E-field
» v = Elat = Vds/L
At high fields, this ceases to be true
» Carriers scatter off atoms
» Velocity reaches vsat
– Electrons: 6-10 x 106 cm/s
– Holes: 4-8 x 106 cm/s
» Better model
μElat
v vsat μEsat
Elat
1
Esat
Linea r Dependence
1.0 VGS = 4
ID (mA)
I D (mA)
VGS = 3
0.5
VGS = 2
VGS = 1
0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0
VDS (V) VGS (V)
Linear dependence
VGS = 2.0V
1.5
ID (A)
0
EE415 VLSI Design
0 0.5 1 1.5 2 2.5
VDS (V)
Leakage Sources
Subthreshold conduction
» Transistors can’t abruptly turn ON or OFF D
Junction leakage D
» Reverse-biased PN junction diode current
S
Gate leakage
» Tunneling through ultrathin gate dielectric S
-8
10 Slope S
-10 Exponential
10
IG
S
» A and B are tech constants
» Greater for electrons
– So nMOS gates leak more
Negligible for older processes (tox > 20 Å) From [Song01]
5
2
4 linear
quadratic 1.5
ID (A)
ID (A)
3
1
2
0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)
-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5
ID (A)
ID (A)
3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)
S D
VGS = -1.5V
-0.2
-0.4
VGS = -2.0V
Assume all variables
ID (A)
-0.6 negative!
VGS = -2.5V
-0.8
-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)
EE415 VLSI Design
Parasitic Resistances
Polysilicon gate
Drain
contact
G increase W LD
VGS,eff
W
S D
RS RD
LS , D
RS , D RSQ RC Drain
W
RSQ is the resistance per square
RC is the contact resistance
Silicide the bulk region
EE415 VLSI Design
The Transistor as a Switch
ID
V GS = VD D
VGS VT Rmid
Ron
S D R0
V DS
VDD/2 VDD
Rpsubs n-source
Rpsubs
p-substrate
Long-channel
approximation
VDS = 5 V VDS
Select k’ and such that best matching is obtained @ Vgs= Vds = VDD
VDS=VDSAT
2
Velocity
1.5
Saturated
ID (A)
Linear
1
VDSAT=VGT
0.5
VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)
EE415 VLSI Design
Technology Evolution
2.10
2.10
Delay (nsec)
1.90
Delay (nsec)
1.90
1.70
1.70
1.50 1.50
1.10 1.20 1.30 1.40 1.50 1.60 –0.90 –0.80 –0.70 –0.60 –0.50
Leff (in m) VTp (V)
fast
FF
» Leff: ____ SF
» Vt: ____
pMOS
TT
» tox: ____
FS
Slow (S): opposite SS
slow
Not all parameters are independent
slow fast
for nMOS and pMOS nMOS
fast
FF
» Leff: short SF
» Vt: low
pMOS
TT
» tox: thin
FS
Slow (S): opposite SS
slow
Not all parameters are independent
slow fast
for nMOS and pMOS nMOS
Cycle time
Power
Subthrehold
leakage
Cycle time S S S S
Power F F F F
Subthrehold F F F S
leakage
>500µm
EE415 VLSI Design
60