ETU 07122

LECTURE_3

Lecture_3 ETU 07122 1

 Lecture_3
 Coverage
• Field-Effect Transistor (FET)
 Structure and principals of operation
 Characteristic curves
 DC biasing
 Analysis under various biasing conditions

 References
• Electronic devices and circuit theory, 7th Ed. by Robert L.
Boylestad & Louis Nashelsky, Chapter 5 & 6
• Electronic devices and circuits, by Theodore F. Bogart, Jr.,
Chapter 7

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 Field-Effect Transistor (FET)
 Introduction
• FET is a three terminals semiconductor device
• FET is a voltage controlled device
• Two main types of FETs
 Junction Field Effect Transistor (JFET or FET)
 Metal-Oxide-Semiconductor FET (MOSFET)
• The MOSFET is the most important component in
modern digital IC, such as
 Microprocessors
 Computer memories

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 FET Continue…
 JFET construction
• There are two types of JFETs
 n-channel
 p-channel
• The basic construction of n-channel JFET is shown in
Fig. 4.1
• There are three terminals
 Drain (D) and Source (S) are connected to n- channel
 Gate (G) is connected to the p-type material
• JFET has two p-n junction, hence, a depletion region
at each junction as shown in Fig. 4.1

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 FET Continue…

Figure 4.1 Structure of an n-channel JFET

• The region of n-material is called the channel
• The transistor shown in Fig. 4.1 is therefore called an n-
channel JFET
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 FET Continue…
 JFET operation (n-channel)

(a) (b)
Figure 4.2 (a) JFET in the VGS = 0V and VDS > 0V, (b) ID versus VDS for VGS
= 0V

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 FET Continue…
From Figure 4.2
• As VDS is increased slightly above zero, ID also
increases as shown in Fig. 4.2 (b)
• As VDS continue to increase, a depletion regions begin
to form in the channel Fig. 4.2 (a)
• Continuing increasing VDS, will cause the depletion
regions to meet at a point in the channel near the
drain end
• This condition is called pinch-off
• Where pinch-off occurs, the gate-to-channel junction
is reversed biased by the value of VDS
• This value is called the pinch-off voltage (VP)
• VP is always a –ve quantity for an N-channel JFET
and a +ve quantity for a P-channel JFET

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 FET Continue…
• Fig 4.2 (b) shows that at pinch-off ID reaches
maximum and it remains at that value as VDS is
increased beyond VP
• This current is called the saturation current and is
designated IDSS
• IDSS – the Drain-to-Source current with the gate
Shorted
• IDSS is the maximum drain current for a JFET and is
defined by the conditions VGS = 0V and VDS = |VP|

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 FET Continue…
 FET Characteristics
• VGS is the controlling voltage of the JFET
• The relationship between ID and VDS can be developed for a
various levels of VGS for the JFET
• For the n-channel device, VGS is made more and more –ve
from its VGS = 0 V level
• The result is to reach the saturation level at a lower level of
VDS as shown in Fig. 4.3 for VGS = -1 V
• The level of ID has been reduced and continue to decrease
as VGS is made more and more -ve
• Also it can be noted from Fig. 4.3 that, VP drop as VGS
becomes more and more –ve
• Finally, the level of VGS = VP will results in ID = 0 mA and the
device will be turned off
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 FET Continue…

Figure 4.3 n-channel JFET characteristics with IDSS = 8mA and VP = -4 V

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 FET Continue…
• The region to the right of pinch-off locus of Fig 4.3 is
called constant-current, saturation, or linear
amplification region
• Within this region the JFET is used as a linear
amplifier
• The region to the left of pinch-off locus of Fig. 4.3 is
called the ohmic or voltage-controlled resistance
region
• In this region the JFET is used as a variable resistor
• In Fig. 4.3, the resistance of the device between drain
and source for VDS < VP is a function of VGS
• The drain-to-source resistance level increases as as
VGS becomes more and more –ve
• Eqn. 4.1 approximate the resistance level in terms of
the applied VGS
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 FET Continue…

Where ro is the resistance with VGS = 0 V

rd is the resistance at a particular level of VGS
 FET Symbol

(a) (b)
Figure 4.4 JFET Symbols: (a) n-channel; (b) p-channel

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 FET DC biasing
• The general relationship that can be applied to the DC
analysis of all FET amplifiers are

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 FET Continue…
• Fixed-bias configuration

 By applying KVL at the input loop

VGS = -VGG……………………………………….(4.5)
 For the output loop
VDS = VDD – IDRD………………………………...(4.6)
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 FET Continue…
• Self-bias configuration

Consider input loop

VGS = - IDRS ……………………………………….(4.7)
Consider output loop
VDS = VDD – ID(RD + RS) ……………………........(4.8)
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 FET Continue…
• Voltage-divider biasing configuration

 Consider input loop

VGS = VG – IDRS ………………………………..(4.9)
 For the output loop, Eqn. 4.8 hold

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 THE END OF
LECTURE 3

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