multiplier 4

declare register A[7:0],Q[7:-1],M[7:0],COUNT[2:0];

declare bus INBUS[7:0],OUTBUS[7:0];
BEGIN : A:=0,COUNT:=0, {c0}
INPUT : M:=INBUS;
Q[7:0]:=INBUS[7:0],Q[-1]:=0; {c1}
TEST1 : if Q[0]Q[-1]=01 then A:=A+M, go to TEST2; {c2}
else if Q[0]Q[-1]=10 then A:=A-M; {c2, c3}
TEST2: if COUNT7=1 then go to OUTPUT,
RIGHTSHIFT: A[7]:=A[7], A[6:0], Q:=A.Q[7:0],
INCREMENT : {c4}
COUNT:=COUNT+1, go to TEST1;
OUTPUT : {c5}
OUTBUS:=A,Q[0]:=0;
OUTBUS[7:0]:=Q[7:0]; {c6}
END : {END}

Fig.3.15
 0
co Multiplier c1
Accumulator register c5 Multiplicand register
0 s
A[7] A A[0] Q[7] Q Q[0] Q[-1] M[7] M M[0]
c4 … … …
c4 wordgate
8 8
8 8
Counter
8 EX-OR
COUNT
c4 C[2] C[1] C[0]
cout Parallel adder cin 8
Q Q Q Q Q Q
c2 8 0
8 8
c0
AND

c5 c6 c1 COUNT7 c0
OUTBUS
8-bit
data INBUS
bus

External BEGIN co Internal

Control control

.. ..
control CLOCK c3
signals unit c6 signals
END

Fig.3.16
 S0
COUNT7=1
Begin
?
No

Yes

BEGIN No Yes Yes

Q[0]=0 Q[0]=0
? ? ?
Yes No No
S1 c0 S3 c2 S5 c2, c4
A:=0, COUNT:=0, A:=A+M, A:=A-M, Phase 0
F:=0; M:=INBUS F:=(Q[0] and M[7]) or F; Q[0]:=0 0

S2 c1 S4 c3 S6 c5
Q:=INBUS A[7]:=F, Phase 1
A[6:0].Q:=A.Q[7:1],
OUTBUS:=A 1
COUNT:=COUNT+1
S7 c6
Phase 2
OUTBUS:=Q 2
S0 END
End
Cycle 0 Cycle 1 to 7 Cycle 8
Fig.B.1
 State Input (BEGIN, Q[0], COUNT7)
Code vector
(y2, y1, y0) 000 001 010 011 100 101 110 111
State
000 S0 S0 S0 S0 S0 S1 S1 S1 S1
END END END END c0 c0 c0 c0
001 S1 S2 S2 S2 S2 S2 S2 S2 S2
c1 c1 c1 c1 c1 c1 c1 c1
010 S2 S4 S4 S3 S3 S4 S4 S3 S3
c3 c3 c2 c2 c3 c3 c2 c2
011 S3 S4 S4 S4 S4 S4 S4 S4 S4
c3 c3 c3 c3 c3 c3 c3 c3
100 S4 S4 S6 S3 S5 S4 S6 S3 S5
c3 c5 c2 c2, c4 c3 c5 c2 c2, c4
101 S5 S6 S6 S6 S6 S6 S6 S6 S6
c5 c5 c5 c5 c5 c5 c5 c5
110 S6 S7 S7 S7 S7 S7 S7 S7 S7
c6 c6 c6 c6 c6 c6 c6 c6
111 S7 S0 S0 S0 S0 S0 S0 S0 S0
END END END END END END END END