Serial Communications

Interface
 Introduction to Serial Communication
Using the serial communication

When using the serial communication we transmit the multi-bit word

bit after bit (when at any given moment only one bit will pass).
Using the parallel communication

 When using the parallel communication, however, the number

of bits will be transmitted at once from one computer to the
second computer
Synchronous and Asynchronous Communication
Synchronous communication

When using the synchronous communication – the information is

transmitted from the transmitter to the receiver:

 in sequence, bit after bit

 with fixed baud rate
 and the clock frequency is transmitted along with the bits
the clock data is recovered separately from the data stream and no
start/stop bits are used. This improves the efficiency of transmission on
suitable channels; more of the bits sent are data.

Asynchronous communication

recover character timing information from the data stream, using

designated "start" and "stop" bits to indicate the framing of each character.
“Start” bit marks the beginning of a new frame.
 “Stop” bit marks the end of the frame.
 Universal
Asynchronous
Receiver-Transmitter
(UART)
UART or USART?
UART or Universal Asynchronous Receiver-Transmitter

 Is a piece of computer hardware that translates between parallel bits of data and
serial bits.
 A UART is usually an integrated circuit used for serial communications over a
computer or peripheral device serial port.
 UARTs are now built into some microcontrollers. Some chips have both
synchronous and asynchronous modes. These are called USARTs (for "universal
synchronous asynchronous receiver-transmitters “)
Enabling Serial Communication

To communicate with external components such as computers or

microcontrollers, the PIC micro uses a USART. This component can be
configured as:

 a Full-Duplex asynchronous system that can communicate with

peripheral devices, such as CRT terminals and personal computers

 a Half-Duplex synchronous system that can communicate with

peripheral devices, such as A/D or D/A integrated circuits, serial
EEPROMs, etc.
To enable the serial communication with PIC micro we must set different
parameters within two registers: TXSTA and RCSTA

The size of this register is one byte (8 bits). TXEN: Transmit Enable bit
Here's a breakdown of the bit roles: 1 = Transmit enabled
0 = Transmit disabled
CSRC: Clock Source Select bit – this bit is
meaningful only in Synchronous communication SYNC: USART Mode Select bit
in Half-Duplex mode. It “determines” if the 1 = Synchronous mode
component is Master (transmitter) or Slave 0 = Asynchronous mode
(receiver). It does not matter in the case of Full-
Duplex mode. BRGH - High Baud Rate Select bit – setting this bit
“determines” the transmission speed (High /
Asynchronous mode: Low). The setting of this bit valid only for
Don’t care. asynchronous mode, and not used for
synchronous mode:
Synchronous mode:
1 = Master mode (clock generated internally from Asynchronous mode:
BRG) 1 = High speed
0 = Slave mode (clock from external source) TX9: 0 = Low speed
9-bit Transmit
Synchronous mode: Unused in this mode.
TX9: 9-bit Transmit Enable bit - this bit lets
select the transmitted frame size 8 or 9-bit TRMT - Transmit Shift Register Status bit
1 = Selects 9-bit transmission 1 = TSR empty
0 = Selects 8-bit transmission 0 = TSR full

TX9D - Place for a 9th bit, Place for a 9th bit, in

the case of transmitting 9-bits.
The size of this register is also 8 bits. The role of
each bit is discussed below:
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures pin RC7/RX/DT
for receiving the information into the PIC, and pin
RC6/TX/CK for transmitting the information from PIC)
0 = Serial port disabled
RX9: 9th -bit Receive Enable bit
1 = enables reception of 9 bit
0 = enables reception of 8 bit
SREN - Single Receive Enable bit - this bit enables or
cancels transmission of packets. In the asynchronous
mode - this bit is not important. The importance of
this bit is only in the synchronous mode (Half-
Duplex) and only when PIC is Master. Asynchronous
mode: Don’t care. Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive This bit is cleared after
reception is complete. Synchronous mode – Slave:
Don’t care.
CREN - Continuous Receive Enable bit Asynchronous
mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN
is cleared (CREN overrides SREN)
0 = Disables continuous receive
ADDEN - Address Detect Enable bit - this bit enables
interrupt only when the frame size is 9-bit. It does
not matter, when the size of the frame is 8-bit.
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and
load of the receive buffer when RSR[8] is set 0 =
Disables address detection, all bytes are received and
ninth bit can be used as parity bit
FERR – Framing Error bit Logic level “1” – means the
STOP bit was not received. In serial communication
we use START bit and STOP bit when transmitting the
information.
1 = Framing error (can be updated by reading RCREG
register and receive next valid byte)
0 = No framing error
OERR - Overrun Error bit Logical level “1” means that
new byte of data was received, while there is still
previous data that did not proceed into the PIC. In this
case, the new received information is lost.
1 = Overrun error (can be cleared by clearing bit
CREN)
0 = No overrun error
RX9D: 9th bit of Received Data, in the case of
receiving 9-bits.
An example of 8-bit transmission:

Suppose we want to transmit the following information: 10110010. This

information is in the size of 8-bit, we will set the TX9 = 0 which enables
transmission of 8-bit data

The information before the transmission will look like this:

8-bit reception:

Now, let’s define the receiver side to receive 8 bit information. To do

so, the register RX9 will be set (RX9D=0). The received 8-bit
information, will be stored in the RSR register, which acts as a
temporary buffer storage.

The received information will look like this:

USB to Serial UART 5V TTL Header Cable

Pin Description

GND Device ground supply pin

CTS Clear to Send input, handshake signal

VCC Power Supply Output to target board

TXD UART Data Transmit, Output

RXD UART Data Receive, Input

RTS Request to Send output, handshake signal

Inter-Integrated Circuit
(I C)
2
 Inter-Integrated Circuit (I2C)
 I2C is a multipoint, open drain, two wire bus (clock and data)
 The SDA(for data) and SCL(for clock) ƒ
 Multiple masters and multiple slaves may co-exist on the bus, each with
their own unique 7-bit address.
 The I2C protocol consists of a START bit followed by a one byte address
(7 bits of address and 1 bit for read/write direction), one or more bytes
of data and a STOP bit.
 invented by Philips Semiconductor (now NXP Semiconductors).
 I2C START/STOP Conditions
 START condition: Signals begin of transfer
 A HIGH to LOW transition on the SDA line while the SCL is HIGH

 STOP condition: Signals end of transfer

 A LOW to HIGH transition on the SDA line while the SCL is HIGH

START/STOP is always generated by the Master

Repeated START condition is allowed–Repeated start is used for

changing the slave, or changing the direction of data transfer
(Send/Receive) for the same slave
I2C Bit Transfer

Clock high, data Clock high, data

stable stable

Clock Clock Clock

low, low, low,
data data data
can can can
change change change
 I2C Data Transfer
 Every byte on the SDA line must be 8-bits long

 Each byte must be followed by an acknowledgement from the

receiver

 Data byte is transferred bit-wise with the MSB as the first bit sent

 A slave can force the master to wait by holding the clock line SCL
LOW
I2C Communication: Master Read Request

The read sequence is as follows: :

[1] The Master Sets The Start Bit Low
[2] The Master Write The Device ID + Read/Write Bit
[3] The Slave Acknowledges With One '0' Bit
[4] The Master Writes The 8-bit Address To Read
[5] The Slave Acknowledges With One '0' Bit
[6] The Slave Writes The 8-Bits At The Address
[7] The Master Acknowledges With One '0' Bit
[8] The Master Sets The Stop Bit At 1 (+5v)
I2C Communication: Master Write Request
The write sequence is as follows:
[1] Master Sets The Start Bit Low (+0v)
[2] Master Write The Device ID + Read/Write Bit
[3] Slave Acknowledges With One '0' Bit
[4] Master Writes The 8-bit Address To Read
[5] Slave Acknowledges With One '0' Bit
[6] Master Sets The Stop Bit At 1 (+5v)
[7] Master Sets The Start Bit Low (+0v)
[8] Master Acknowledges With One '0' Bit
[9] Master Sends 8 data bits
[9] Slave writes the data to memory
[10] Master Sets Not-Acknowledge Bit
(+5v)
[11] Master Sets The Stop Bit At 1 (+5v)
SMBus & PMBus
 System Management Bus (SMBus)
Whereas I2C is wide open, SMBus strictly defines the data packets into a few
allowable protocols such as “Write Byte/Word”, “Block Write/Read” and so on.

SMBus also adds robustness to the basic I2C specification with the
introduction of a bus timeout and the optional Packet Error Checking (PEC)
protocol.

SMBus addresses follow the I2C format, however one address is reserved for
an SMBus protocol called Alert Response Address which allows the Master to
quickly find out which Slave signaled the SALERT# line.

SMBus Device Connections

 Power Management Bus (PMBus)
 An open standard power-management protocol

 Allows for communication between devices based on both analog

and digital technologies

 Provides true interoperability, which will reduce design complexity

and shorten time to market for power system designers

 The current PMBus specification is version 1.2 and was released in

2010. In addition, PMBus adds a further data packet protocol

 The “GROUP” command which allows multiple devices to be sent

commands in a single large data packet that is the concatenation of
address, command and data to each device.
PMBus Device Connections
Linear Data Format
 The Linear Data Format is a two byte value with: An 11 bit, two’ ’s complement mantissa
and A 5 bit, two’’s complement exponent (scaling factor).

 Typically used for commanding and reporting the parameters such as (but not only) the
following: Output Current, Input Voltage,Input Current, Operating Temperatures,Time
(durations), Energy Storage Capacitor Voltage

Expresses numbers according to the formula X = Y.2 N, where Y is the mantissa and N is
the exponent. This is encoded within two bytes of data where the first 5 bits are the
exponent (N) and the remaining 11 bits are mantissa (Y)
Direct Data Format
 DIRECT format data is a two byte, two’ ’s complement binary integer. DIRECT
format data may be used with any command that sends or reads a parametric
value. If a PMBus device uses DIRECT form data, this shall be clearly described in
the product literature.
PMBus Command: Read/Write Byte without PEC
PMBus Command: Read/Write Word without PEC
Common PMBus Commands: OPERATION Command

The OPERATION command is used to turn the unit on and off in conjunction with
the input from the CONTROL pin.
It is also used to cause the unit to set the output voltage to the upper or lower
MARGIN VOLTAGEs.
Examples:
FAN_CONFIG_1_2 Command

The FAN_CONFIG_1_2 is used to configure up to two fans associated with one

PMBus device.
The first of the configuration tells the PMBus device whether or not a fan
associated with position 1 (or 2) is installed.
The second part of the configuration tells the device whether the fan speed
commands are in RPM or PWM duty cycle (in percent).
The third part of the configuration data tells the PMBus device the number of
tachometer pulses per revolution each fan provides.
Example:
FAN_COMMAND_n Command
 The FAN_COMMAND_1, FAN_COMMAND_2, FAN_COMMAND_3 and
FAN_COMMAND_4 commands are used to adjust the operation of up to four fans
contained in the PMBus device or in the host system
 The command may be in RPM or duty cycle, as set by the
FAN_COMMAND_CONFIG command. The default value is specified in the device
manufacturer product literature.

Example:
Common PMBus Commands: STATUS Command

 STATUS_BYTE returns more critical faults. STATUS_WORD returns two bytes

of fault information. The low byte of STATUS_WORD is the same register as the
STATUS_BYTE command.
Example: Over-voltage Status
Example: Over-current Status
Example: Over-temperature Status