Design & Implementation of

High Efficient
Carry Select Adder

Submitted by:
Gorbi Domi I (20610106028)
C.Maria Kigin (20610106055)

Under the guidance of:

Mr.R.Singaravelu., M.Tech

04-Apr-14 FINAL REVIEW

OVERVIEW:
 Abstract
 Introduction
 Literature Survey
 Conventional Circuits and disadvantages
 Proposed System and advantages
 Comparisons
 Mode of implementation

04-Apr-14 FINAL REVIEW

 Abstract:
1. Carry Select Adder(CSA) is one of the fastest adder
used in many data processing processors.

2. Main disadvantage of carry select adder is its large

area.

3. This project is to reduce the area and power

consumption of carry select adder and thereby
increase its efficiency.

04-Apr-14 FINAL REVIEW

 Introduction:
We have to plane to reduce the area of carry select adder.

In CSA more than one stages are used to reduce the delay.

After the first stage , each stage have two RCA(ripple carry
adder). One for Cin=0 and other for Cin=1.

We have plan to produce the output of two RCA by using one
RCA gate area.

This will reduce the space as-well-as power consumption of

CSA.

04-Apr-14 FINAL REVIEW

LITERATURE SURVEY:

Author Title Description Year

O. J. Bedrij Carry-select adder A large, extremely fast 1962
digital adder with sum
selection and multiple-
radix carry.
T. Y. Ceiang and Carry-select adder Its a carry select adder 1998
M. J. Hsiao using single ripple scheme using an add-one
carry adder circuit to replace one
carry-ripple adder.
Y. Kim and L.-S. 64-bit carry-select A multiplexer-based add- 2001
Kim adder with one circuit is proposed to
reduced area reduce the area with
negligible speed penalty.

04-Apr-14 FINAL REVIEW

Author Title Description Year
Y. He, C. H. An area efficient In this paper, an area 2005
Chang, and J. Gu 64-bit square root efficient square root CSL
Carry-select adder scheme based on a new
for low power first zero detection logic is
applications proposed.
B. Ramkumar, ASIC A circuit is proposed which 2010
H.M. Kittur, and implementation performs fast addition,
P. M. Kannan of modified faster while maintaining low
carry save adder power consumption and
less area.

04-Apr-14 FINAL REVIEW

 EXISTING SYSTEM

This work uses a simple and efficient gate-level modification to

significantly reduce the area and power of the CSLA.

Based
on this modification 8-, 16-, 32-, and 64-b square-root CSLA
(SQRT CSLA) architecture have been developed.

The
design has reduced area and power as compared with the regular
SQRT CSLA with an increase in the delay.

Thiswork evaluates the performance of the proposed designs in terms of

delay, area, power, and their products by hand with logical effort and
through custom design and layout in 0.18- m CMOS process technology.

The results analysis shows that the proposed CSLA structure is better
than the regular SQRT CSLA.
04-Apr-14 FINAL REVIEW
EXISTING SYSTEM(CONTD.)

The CSLA is not area efficient because it uses multiple pairs of

Ripple Carry Adders (RCA) to generate partial sum and carry.

The addition of second addition Cin=1 is one greater than the

first addition Cin=0 so we use binary to excess-1 counter (BEC)
instead of second RCA.

The main advantage of this BEC logic comes from the lesser
number of logic gates.

04-Apr-14 FINAL REVIEW

 Base circuit

04-Apr-14 FINAL REVIEW

 4-Bit addition stage
a[3:0] b[3:0]

4 bit RCA

Cin=0

Carry s3 s2 s1 s0
a[3:0] b[3:0]

4 bit RCA

Cin=1

Carry s3 s2 s1 s0
04-Apr-14 FINAL REVIEW
Disadvantage:
1. Full adder require 2 HA and an OR gate, so 4 bit Ripple carry
adder require 16 HA and 8 OR gate.

2. Hence it requires large area.

3. Power consumption is also high due to its large area.

04-Apr-14 FINAL REVIEW

 Conventional circuit output window

04-Apr-14 FINAL REVIEW

 PROPOSED SYSTEM
 In the conventional system they have managed to reduce the power consumption and
area but with a considerable addition in delay

 This project deals with reducing the area as well as power consumption without any
addition of delay.

 In this system we use half adders instead of RCA and BEC to reduce area and power
without changing the delay.

 The base circuit uses two N-bit RCA in every stages. Two N-bit RCA comprises of
(4*N) half adders and (2*N) OR gates which is reduced to just 10 half adders and 7
OR gates in our circuit.

 This proves a large improvement that area is reduced 30-35% in every stage without
any change in delay.
04-Apr-14 FINAL REVIEW
 Modified Circuit for 4-bit addition
Output for cin=1
s1 s2 s3

s0
HA HA HA

Carry 1

a0 a1 a2 a3
b0 HA HA HA HA
b1 b2 b3

Carry 0

HA HA HA

s0 s1 s2 s3
Output for cin=0

04-Apr-14 FINAL REVIEW

 Schematic Diagram For Proposed Circuit

04-Apr-14 FINAL REVIEW

 Delay Estimation Window

04-Apr-14 FINAL REVIEW

 Proposed circuit output window

04-Apr-14 FINAL REVIEW

 Advantages:
Instead of 16 half adder, only 10 half adder is used.

This will reduce the area of the circuit.

Reducing the area will also reduce the power

consumption of the circuit.

The delay remained unchanged.

04-Apr-14 FINAL REVIEW

POWER COMPARISON:

Flip Flops Total gate (4-bit) Power(µw) Time (in ns)

Base circuit 80 52.7 12.46

Proposed circuit 68 47.1 12.46

04-Apr-14 FINAL REVIEW

 Comparison Chart:

80

70

60

50

40
proposed circuit
30 base circuit

20

10
base circuit
0
total gate proposed circuit
time(in nano
secound) power(in micro
walt)

04-Apr-14 FINAL REVIEW

 Mode of Implementation:

• XILINX ISE

• Logic Gates (Hardware)

04-Apr-14 FINAL REVIEW

CONCLUSION:
 A This paper presents a highly efficient form of carry select adder which
has improvement in reducing the area as-well-as power consumption without
changing the delay.

 Half adder is used in the circuit instead of using 2 RCA in each stage which
will reduce area and power consumption.

 In this circuit Half adders and OR gates are used instead of using two RCA
blocks for finding both Cin=0 & Cin=1. This will reduce the area and power
consumption of the circuit without any change in the delay.

 This modified carry select adder is simulated using Xilinx10.1 simulation

software.

 The circuit was implemented in PCB board using logic gates.

04-Apr-14 FINAL REVIEW
References:
 B. Ramkumar, H.M. Kittur, and P. M. Kannan, “ASIC implementation
of modified faster carry save adder,” Eur. J. Sci. Res., vol. 42, no. 1, pp.
53–58, 2010.

 Y. He, C. H. Chang, and J. Gu, “An area efficient 64-bit square root
carry-select adder for low power applications,” in Proc. IEEE Int. Symp.
Circuits Syst., 2005, vol. 4, pp. 4082–4085.

 Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,”
Electron. Lett., vol. 37, no. 10, pp. 614–615, May 2001.

 T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple

carry adder,” Electron. Lett., vol. 34, no. 22, pp. 2101–2103, Oct. 1998.

 O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron. Comput., pp. 340–344,

1962.

04-Apr-14 FINAL REVIEW

Thank You