The document describes three questions about digital logic circuits:
1) Designing a serial decrementer circuit using a JK flip-flop and one gate to decrement the value in a 4-bit shift register by 1 after 4 clock cycles.
2) Modifying a 4-bit twisted ring counter circuit to skip the 1111 state.
3) Designing a 3-bit arbitrary sequence counter using D flip-flops and gates to count in the sequence 3->2->1->5->7->0->6->4.
The document describes three questions about digital logic circuits:
1) Designing a serial decrementer circuit using a JK flip-flop and one gate to decrement the value in a 4-bit shift register by 1 after 4 clock cycles.
2) Modifying a 4-bit twisted ring counter circuit to skip the 1111 state.
3) Designing a 3-bit arbitrary sequence counter using D flip-flops and gates to count in the sequence 3->2->1->5->7->0->6->4.
The document describes three questions about digital logic circuits:
1) Designing a serial decrementer circuit using a JK flip-flop and one gate to decrement the value in a 4-bit shift register by 1 after 4 clock cycles.
2) Modifying a 4-bit twisted ring counter circuit to skip the 1111 state.
3) Designing a 3-bit arbitrary sequence counter using D flip-flops and gates to count in the sequence 3->2->1->5->7->0->6->4.
The document describes three questions about digital logic circuits:
1) Designing a serial decrementer circuit using a JK flip-flop and one gate to decrement the value in a 4-bit shift register by 1 after 4 clock cycles.
2) Modifying a 4-bit twisted ring counter circuit to skip the 1111 state.
3) Designing a 3-bit arbitrary sequence counter using D flip-flops and gates to count in the sequence 3->2->1->5->7->0->6->4.
Tutorial : 12 Registers and counters Q1. A serial decrementer block with a 4-bit shift register is shown in the figure below. 4-bit shift register is initially loaded with a binary value (say M) other than 0000. Design the serial decrementer circuit (as Mealy sequential Circuit) using only one JK Flip-flop (which has both Q and Q’ outputs) and one logic gate, such that after 4 clock cycles the shift register contains binary value equal to M-1. (e.g., If shift register contains 1101 initially then after 4 clock cycles the shift register should contain 1100) Q2. Modify the circuit diagram of a 4-bit twisted ring counter such that it skips the 1111 state. Draw the modified circuit.
Q3. Design a three-bit arbitrary sequence counter which counts in the following sequence: