Chapter 2

The Central Processing Unit

 Outline
 Instruction set Characteristics & Function
 Interrupts

 Machine Instruction Characteristics

 Instruction set Design
 Instruction Cycle
 Processor Structure and Function
 RISC, CISC
 Bus Inter-connection
 Computer Arithmetic

2
 Instruction Set Characteristics & Function
• The operation of the processor is determined by the instructions it executes, referred
to as machine instructions or computer instructions.
• The collection of different instructions that the processor can execute is referred to
as the processor’s instruction set.
Elements of a Machine Instruction
• Each instruction must contain the information required by the processor for execution.
• Operation code: Specifies the operation to be performed (e.g., ADD, I/O). The operation is
specified by a binary code, known as the operation code, or opcode.
• Source operand reference: The operation may involve one or more source operands, that is,
operands that are inputs for the operation.
• Result operand reference: The operation may produce a result.
• Next instruction reference: This tells the processor where to fetch the next instruction after the
execution of this instruction is complete.
3
Instruction set Architecture & Characteristics

Fig 2.1 Instruction state cycle Diagram

• The address of the next instruction to be fetched could be either a real address or a virtual address, depending on
the architecture.

• Generally the distinction is transparent to the instruction set architecture.

4
Instruction set Architecture & Characteristics
• Where can be Source and result operands located?

Source and Result operands can be found in one of the four areas:
Main or Virtual Memory, Processor Register,
• Immediate: The value of the operand is contained in a field in the instruction being executed.
• I/O device: The instruction must specify the I/O module and device for the operation. If memory-mapped I/O is
used, this is just another main or virtual memory address.

Instruction Representation

5
Instruction set Architecture & Characteristics
Instruction Representation(Cont..)
• Within the computer, each instruction is represented by a sequence of bits.

• The instruction is divided into fields, corresponding to the constituent elements of the instruction.

• During instruction execution, an instruction is read into an instruction register (IR) in the processor.

• The processor must be able to extract the data from the various instruction fields to perform the required
operation.

• Since it is difficult to deal with the binary representation of machine instructions, it become common practice to
use Symbolic representation of machine instructions.

• Opcodes are represented by abbreviations, called mnemonics, that indicate the operation.

Examples are

ADD Add MUL Multiply LOAD Load data from memory

SUB Substract DIV Divide STOR Store

6
Instruction Representation(Cont..)

• Operands are also represented symbolically. For example, the instruction

ADD R, Y

Means add the value contained in data location Y to the contents of register R.

Y refers to the address of a location in memory, and R refers to a particular register.

Note that the operation is performed on the contents of a location, not on its address.

Instruction Types
• the set of machine instructions must be sufficient to express any of the instructions from a high-level language.

Categories of Instruction Types

 Data Processing

Arithmetic and Logic Instructions

7
 Instruction Types
Categories of Instruction Types…
 Data processing
 Arithmetic and logic instructions

 Data Storage
 Memory Instructions

 Data Movement
 I/O Instructions

 Control
 Test and Branch Instructions

8
 Instruction Set Design
• One of the most interesting, and most analyzed, aspects of computer design

• It affects so many aspects of the computer system.

• The instruction set

 Defines many of the functions performed by the processor
 has a significant effect on the implementation of the processor’
 the programmer’s means of controlling the processor .
 programmer requirements must be considered in designing the instruction set.

• most important of these fundamental design issues include the following:

Operation Repertoire: How many ops, what can they do and how complex they are
Data types: various types of data upon which operations are performed

Instruction format: Instruction length (in bits), number of addresses, size of various fields, and so on

Registers: Number of processor registers that can be referenced by instructions, and their use.

Addressing: modes of addressing operands

9
 Types of Operands
• Machine instructions operate on data. The most important general categories of data are

Numbers

Binary Integer, Binary Fixed Point, Floating point and decimal

Characters

ASCII code, Unicode, etc

Boolean

Bits or flags

A group of bit where each bit has information

10
 Types of Operations
• A useful and typical categorization is the following:

 Data transfer
 Arithmetic
 Logical
 Conversion
 I/O
 System control
 Transfer of control

11
 Data Transfer
 Most fundamental type of instructions
 Must specify the following things
 Location of source and destination operands
 memory, register …
 Length of data to be transferred
 Full word, half word …
 Addressing mode of each operand
 E.g.
 Move, Store, Load, Push, Pop
 In terms of CPU action
 data transfer operations are the simplest type

12
 Arithmetic
 Performed by ALU
 Basic arithmetic operations provided by most
• machines are:
 Add, Subtract, Multiply, Divide
 Signed Integer
 Floating point

 May include
 Increment
 Decrement
 Negate
 Absolute

13
 Logical
 Operations that manipulate individual bits of a word
 Bitwise operations
 AND, OR, exclusive-OR (XOR)
 NOT (one’s complement)
 In addition a variety of shifting and rotating functions
 Logical shift
 Shifts bits of word either to the left or right
 On one end the bit shifted out is lost
 Arithmetic shift
 Treats the data as a signed integer and does not shift the sign bit
 Rotate/Cyclic shift
 Preserves all of the bits being operated on

14
SHIFT AND ROTATE OPERATIONS
0

logical
shift
shift in 0

arithme
tic
shift
keep sign !

rotate
15
 Conversion
 Change the format of data or operate on the format of data
 Binary to Decimal
 ASCII to EBCDIC

 E.g. Binary to BCD

 Binary 00001111 (1510)
• packed BCD 0001 0101
1 5

16
 Input/Output
 Transfer data
 from the computer to peripheral devices
 From peripheral devices to the computer system
 To be seen in detail in another chapter

17
 System Control
 Reserved for use by the operating system
 Instructions executed while the processor is in certain privileged
mode
 Privileged instructions
 CPU needs to be in specific state

18
 Transfer of Control
 Alter the flow of program
 i.e. change the sequence of instruction execution
 Update the PC to a specific address
 Most common such type of operations are:
 Branch, Skip, Procedure call

19
 Transfer of Control
 Branch
 Also called jump instruction
 Its operand is the address of the next instruction to be fetched and executed
 Two types of branches
 Conditional and Unconditional
 Conditional Branch
 A branch is made if certain condition is met
 E.g.
 BRP X
 Branch to instruction at location X if result is positive
 BRZ X
 Branch to instruction at location X if result is zero
 BRE R1,R2,X
 Branch to X if contents of R1 is equal to contents of R2

20
 Transfer of Control
 Unconditional branch
 E.g.
 BR X
 Branch to instruction at location X

Branch Instructions

21
 Transfer of Control
 Skip
 Implies that the next instruction be skipped
 Contains an implied address
 Can be of two types:
 Unconditional
 Skip (i.e. unconditionally increment PC to skip the next instruction)

 Conditional

 Test some condition and skip if met/satisfied

 E.g. Increment and skip next instruction if result is zero
ISZ R1  increment & skip if zero
Branch X  skip this if result was zero
ADD A
Procedure call
•  [Reading Assignment]
22
 Addressing Modes
• The manner in which each address field specify operand location

• Notations:
• A = Contents of an address field in the instruction
• R = Contents of an address field in the instruction that refers to a register
• (X) = Contents of memory location X or register X
• EA =Effective address of the location containing the referenced operand

23
 Addressing Modes
 Types of addressing modes
 Immediate
 Direct
 Indirect
 Register
 Register Indirect
 Displacement
 Stack

24
 Immediate Addressing Mode
 The instruction itself contains the operands value
 Operand is part of instruction

 Operand = A
 E.g. ADD 5
 Add 5 to contents of accumulator
 5 is operand

 No additional memory reference required after the fetch of the

instruction itself
 The value that can be specified is limited
 Size/value of the operand is limited/limited range
 Fast

25
Immediate Addressing Mode

Opcode Operand

26
 Direct Addressing
 Address field contains address of operand
 Effective address EA = A
 Operand = (A)
 E.g. ADD A
 Add contents of memory location A to accumulator
 One more memory access needed to fetch the operand
 No additional calculations required to work out effective address
• Number of Memory locations that can be referenced are limited, due to the limited width of the
field.
Limited address space
• Common on earlier generation of computers

27
Direct Addressing Diagram

28
 Indirect Addressing
 A (the address field) refers to a memory location which contains the
address of operand
 Multiple (two) memory accesses to find operand
 Fetch EA
 Fetch operand
 Access the memory twice, hence slower
 EA = (A)
 Operand = ((A))
 E.g. ADD (A)
 Look in A, find address (A) and look there for operand
 Range of EA increased
 Large address space
 2n ,where n = word length

29
Indirect Addressing Diagram

30
 Register Addressing
 Similar to direct addressing
 The address field refers to a register than a main memory address
 EA = R
 Operand = (R )
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
 No memory access required
 Very fast execution
 Very limited address space
 Small number of registers can be referenced

31
Register Addressing Diagram

32
 Register Indirect Addressing
 Similar to indirect addressing mode
 Operand is in memory pointed to by contents of register R
 EA = (R)

 Operand =((R ))

 Large address space (2n)

 Where n is the width of the register
 Address space limitation overcome
 Uses one less memory access than indirect addressing

33
Register Indirect Addressing Diagram

34
 Displacement Addressing
 Very powerful addressing mode
 Combines
 direct addressing and
 Register indirect addressing
 Instruction needs to have two address fields
 At least one of which is explicit
 EA = A + (R)
 Address field hold two values
 A = base value
 R = register that holds displacement
 or vice versa

35
Displacement Addressing Diagram

36
 Relative Addressing
 A version of displacement addressing mode
 Implicitly references the PC register
 R = Program counter, PC
 EA = A + (PC)
 Saves bits

37
 Base Register Addressing
 Referenced register contains memory address
 R holds pointer to base address

 Address field contains the displacement from that address

 A holds displacement

 Exploits locality of memory references

38
 Indexed Addressing
 Address field contains memory address
 A = base
 The referenced register contains a displacement from that address
 R = displacement
 EA = A + ( R )
 Good for accessing arrays and performing iterative operations.

Auto Indexing
Increment and Decrement
Read Computer Architecture & Organization[Author William
Stallings, page 412

39
 Indexed Addressing
 Combinations
Indirect addressing with indexing
 Post indexing
 The indexing performed after the indirection
•  EA = (A) + (R)
 Good to access a block of data of a fixed format
 Pre indexing
 The indexing performed before the indirection
•  EA = (A+(R))
 Used to construct a multiway branch table

40
STACK ADDRESSING
 A stack
 The stack mode of addressing is a form of implied
addressing
 The machine instructions need not include a memory
reference but implicitly operate on the top of the
stack

41
INSTRUCTION FORMAT
 It defines the layout of the bits of an instruction,
in terms of its constituent parts

 More that one format used in a given instruction

set

 What are the factors affecting the

instruction format ?
 READING ASSIGNMENT!!!

42
3.4 INSTRUCTION CYCLE REVISITED
 Instruction cycle so far consists of the
following sub cycles:
 Fetch
 Execute
 Interrupt

 Additional sub cycle to be added:

 Indirect cycle

43
INSTRUCTION CYCLE ,REVISED …
 Indirect addressing
 May require memory access to fetch operands
 Indirect addressing requires more memory accesses
 Can be thought of as additional instruction subcycle

44
3.5 INSTRUCTION CYCLE DATA FLOW
 The exact sequence of events during an
instruction cycle depends on the design of the
CPU

 In general terms, assuming a CPU that employs

the following registers
 MAR
 MBR
 PC
 IR
 The possible Data Flow is indicated next 45
DATA FLOW (INSTRUCTION FETCH)
 Fetch
 PC contains address of next instruction
 Address moved to MAR
 Address placed on address bus
 Control unit requests memory read
 Result placed on data bus, copied to MBR, then to IR
 Meanwhile PC incremented by 1

46
DATA FLOW (FETCH DIAGRAM)

47
DATA FLOW (DATA FETCH)
 IR is examined
 If indirect addressing, indirect cycle is performed
 Right most N bits of MBR transferred to MAR
 Control unit requests memory read
 Result (address of operand) moved to MBR

48
DATA FLOW (INDIRECT DIAGRAM)

49
DATA FLOW (EXECUTE)
 May take many forms
 Depends on instruction being executed

 May include
 Memory read/write
 Input/Output
 Register transfers
 ALU operations

50
DATA FLOW (INTERRUPT)
 Simple and Predictable
 Current PC saved to resumption after
allow interrupt
 Contents of PC copied to MBR
 Special memory location (e.g. stack
pointer) loaded to MAR
 MBR written to memory
 PC loaded with address of interrupt
handling routine
 Next instruction (first of interrupt handler)
can
be fetched 51
DATA FLOW (INTERRUPT DIAGRAM)

52
 3.6 PROCESSOR STRUCTURE AND
FUNCTION
 Processor Organization
 To understand the organization of the CPU,
recall the requirements placed on the CPU:
 Fetch instruction
 Interpret instruction

 Fetch data

 Process data

 Write data

 To do all these things

 Processor needs to store data temporarily
 Temporary data storage locations --- Registers
--- are needed 60
PROCESSOR ORGANIZATION…
 Simplified view of a CPU
 Indicates its connection to the system via the system
bus

54
PROCESSOR ORGANIZATION…
 Detailed view of a CPU
 Indicates
 Data transfer and logic control paths
 Internal processor bus

 Used to transfer data b/n the ALU and various registers

55
Bus Organization for CPU Registers
R1
R2
R3
R4
R5
R6
R7

LD SELA MUX MUX SELB

3x8 A B
Decoder
OPR
ALU
SELD

56
 Bus Organization for 7 CPU Registers
• 2 MUX : select one of 7 register or external data input by SELA and SELB
• BUS A and BUS B : form the inputs to a common ALU

• ALU : OPR determine the arithmetic or logic micro operation

• The result of the micro operation is available for external data output and also goes into the
inputs of all the registers

• 3 X 8 Decoder : select the register (by SELD) that receives the information from ALU

57
 Bus Organization for 7 CPU Registers
• Binary selector input : R1  R 2  R3
• 1) MUX A selector (SELA) : to place the content of R2 into BUS A
• 2) MUX B selector (SELB) : to place the content of R3 into BUS B
• 3) ALU operation selector (OPR) : to provide the arithmetic addition R2 + R3
• 4) Decoder selector (SELD) : to transfer the content of the output bus into R1
• Control Word
• 14 bit control word (4 fields) :
• SELA (3 bits) : select a source register for the A input of the ALU
• SELB (3 bits) : select a source register for the B input of the ALU
• SELD (3 bits) : select a destination register using the 3 X 8 decoder
• OPR (5 bits) : select one of the operations in the ALU
• Encoding of Register Selection Fields :
• SELA or SELB = 000 (Input) : MUX selects the external input data
• SELD = 000 (None) : no destination register is selected but the contents of the output bus are available in the external
output
• Encoding of ALU Operation (OPR) :

• Examples of Micro operations :

• TSFA (Transfer A) : R7  R1, External Output  R 2, External Output  External Input
• XOR : R5  ( XOR R5  R5)
58
General Register Organization

59
REGISTER ORGANIZATION
 Registers
 CPU must have some working space
 Temporary storage
 Top level of memory hierarchy
 Number and function vary between processor designs
 One of the major design decisions

60
REGISTER ORGANIZATION…
 Registers classified into two groups:
 User visible registers:
 Can be referenced by assembly language instructions

 Control and status registers:

 Used by control unit to control the operation of the CPU

61
USER VISIBLE REGISTERS
 Can be categorized as follows:
 General purpose registers
 Data registers
 Address registers
 Condition codes

62
USER VISIBLE REGISTERS…
 General Purpose Registers
 Can be assigned variety of function by
the
programmer
 May be true general purpose
 May be restricted
 May be used for data or addressing

 Data Registers
 Used only to hold data
 Accumulator
63
USER VISIBLE REGISTERS…
 Address registers
 Hold addresses
 Can be
 General purpose or
 Devoted to particular addressing mode

 Index registers, stack pointer, segment register

64
CONDITION CODES
 Sets of individual bits , also called flags
 Each bit set by CPU hardware as the result
of
operations:
 E.g. Arithmetic operation results could be
 Positive, negative, zero, overflow
 Can be read (implicitly) by programs
 e.g. Jump if zero
 Can not (usually) be set by programs

65
CONTROL & STATUS REGISTERS
 Refers to different registers employed to
control the operation of the CPU
 Most not visible to the user

 Register essential during instruction cycle are

 Program Counter (PC)
 Instruction Register (IR)
 Memory Address Register (MAR)
 Memory Buffer Register (MBR)

66
CONTROL & STATUS REGISTERS…
 Program Status Word (PSW)
 A register that contain status information
 Usually contains
 Condition codes
 Status information
 Common fields or flags include
 Sign, zero, carry, equal, overflow, interrupt
supervisor, enable/disable

 Note that CPU design and Operating

system design are closely linked
67