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University of Energy and Natural Resources,

Sunyani
Institute of Distance Learning
Dept. of Comp. & Elect. Eng.
ELNG 301– Microprocessor

A. QUANSAH

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Chapter 0 – Course details
Objective
◦ Provide an understanding of the operation, programming and
application of the standard peripheral interfaces found on modern
microcontrollers used in embedded systems. PIC18xxxx family will
be treated.
Content
◦ Architecture  Von Neumann and Harvard
◦ Number representation  Binary, BCD, fixed-point binary, etc
◦ Arithmetic and logic operations
◦ Memory  flip-flops, read/write timing diagrams, tri-state, etc
◦ PIC18LF8722 instruction set

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Chapter 0 – Course details
Content
◦ Digital interfacing  ADC, DAC, Schmitt trigger buffer, etc
◦ Assembly Language
◦ Software Language
◦ Software development tool
◦ Bit of C programming
Recommended books
◦ Myke Predko 2007. Programming and Customizing the PIC
Microcontroller. ISBN-10: 00714728781 ISBN-13: 978-0071472876
| Edition: 3
◦ Han-Way Huang. An Introduction to Hardware and Software
Interfacing. ISBN 13: 9781401898120

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Computer Families
Computers implementation that share the same instruction set
architecture is group under the same family such as IBM 360 family
and VAX family of computers
Members of computer family can run the same programs.
Different family members may use memories that differ in their
cycle and access times
◦ Different clock rate and faster components

Upward compatibility – the ability of the higher performance

members of a computer family to execute the same programs that
the lower performance members execute is called
Advantage of upward compatibility
◦ Existing software can run on newer more powerful models within the same computer
family

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Classification of computer architecture
Von Neumann Machines
Single path between main memory and the CPU
◦ Single path  major bottleneck in the VN architecture

Basic hardware subsystem

◦ A CPU
◦ Main memory system
◦ I/O system
Programs and data are stored in
single memory  instruction are set
to differentiate between the two
Instruction are executed
sequentially unless altered
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Microprocessor and Microcontroller
Microprocessor
◦ is an IC which has only the CPU inside them.
◦ These microprocessors don’t have RAM, ROM, and other peripheral on
the chip
◦ Application of microprocessor includes Desktop PC’s, Laptops, notepads

Microcontroller
◦ Microcontroller has a CPU, in addition with a fixed amount of RAM, ROM
and other peripherals all embedded on a single chip
◦ Microcontrollers are designed to perform specific tasks. Specific means
applications where the relationship of input and output is defined
◦ Depending on the input, some processing needs to be done and output is
delivered

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Microprocessor and Microcontroller
Microprocessor
◦ is an IC which has only the CPU inside them.
◦ These microprocessors don’t have RAM, ROM, and other peripheral on
the chip
◦ Application of microprocessor includes Desktop PC’s, Laptops, notepads

Microcontroller
◦ Microcontroller has a CPU, in addition with a fixed amount of RAM, ROM
and other peripherals all embedded on a single chip
◦ Microcontrollers are designed to perform specific tasks. Specific means
applications where the relationship of input and output is defined
◦ Depending on the input, some processing needs to be done and output is
delivered

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Classification of computer architecture

Von Neumann Machines

Single path between main memory and the CPU
◦ Single path  major bottleneck in the VN architecture

Major subsytems with CPU

◦ the control unit (CU) : which selects and interprets
machine instructions and coordinates the various parts
of the computer in executing instructions.
◦ the arithmetic logic unit (ALU): which performs
arithmetic, logical and shift operations on the operands
and generates the results.
◦ a register set: which serves as internal storage within
the CPU to hold operands and intermediate values
during instruction fetch and execution

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Classification of computer architecture
Harvard architecture
◦ Base on VN machine or Princeton
architecture
◦ Separate memory for instruction and
data
This architecture is used to denote
computer system that contains
separate pathways for instructions
and data independent of whether
separate memories are used.

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Classification of computer architecture

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Computer Organization
CPU
◦ Function as the brain
◦ It fetches instruction set from the
memory of the computer and
execute them one after another
◦ Instructions and data read from
memory are temporarily held in
registers while they are operated
on by the computer
◦ Registers are storage cells located
inside the CPU and are the faster
form of memory

Registers
◦ Storage cells in CPU and it’s much
faster than the main memory
◦ Parallel wires use to transmit
information
◦ Address, data and control signals
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Components of a computer

The processor gets instructions

and data from memory;
Input writes data to memory,
and output reads data from
memory.
Control sends the signals that
determine the operations of the
datapath, memory, input, and
output.

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Computer Organization
Registers
◦ Storage cells in CPU and it’s much faster than
the main memory
◦ Parallel wires use to transmit information
 Address, data and control signals
ALU
◦ Responds to signal from control unit
◦ Perform required operation on the operand to
produce the necessary output
◦ The operand and resulting output is stored in a
register
◦ The control unit is responsible for decoding
instructions and generating the signals
necessary to cause the other components to
perform the actions called for by the instruction.

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Computer Org. cont’d – single-register design

Data path of a typical von Neumann

machine – Single-register design
Employs single register called
accumulator.
The accumulator holds one operand
during execution of an instruction
Second operand is stored in memory Typical instruction
via data bus LDA X
ALU output is either sent back to data ADD Y
bus or the accumulator for further STA Z
processing BGE P1

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Computer Org. cont’d – multiple-register design
Allows for fast register-
to-register operation
Other registers can be
used for direct and
indirect addressing and
indexing
It allow machine to
implement stack with the
CPU  Operands are not
access explicitly as in single
register
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Computer Org. cont’d – multiple-register design
Allows for fast register-
to-register operation
Other registers can be
used for direct and
indirect addressing and
indexing
• It allow machine to implement
stack with the CPU 
Operands are not access
explicitly as in single register
• Simple instruction implores
pipeling techniques>
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Characteristics of RISC and CISC machines
RISC
Simple instructions taking 1 cycle
Only LOADS/STORES reference memory
Highly Pipeline
Instructions executed by hardware
Fixed format instructions
Few instructions and addressing modes
Complexity is in the compiler
Multiple register sets
CISC
Complex instructions taking multiple cycle
Any instruction may reference memory
Less pipelined (some are not pipelined at all)
Instructions are interpreted by microcode
Variable format used for instructions
Numerous instructions and addressing modes
Complexity is in the microcode
Single register set
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Load and Store Operation – PIC18xxxx
Data movement
instructions
Source of instruction
does not change only
destination In a load operation the
processor copies data into
a register
In a store operation the
processor copies data
from a register into a
memory location
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 Load and Store Instructions

Example of instruction set

include ADDWF, MOVLW,
MOVLW

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PIC18xxxx memory organization
Memory consists of a sequence of directly
addressable "locations."
A memory location is referred to as an information
unit. A memory location in the PIC18 holds eight
bits of information.
Eight bits of information are called a byte.
Sometimes one must deal with four bits of
information at a time. Four bits of information are
called a nibble.
A memory location can be used to store data,
instruction, the status of peripheral devices, and so
on. 21
PIC18xxxx memory organization
Each location in memory has an address that must
be supplied before its contents can be accessed.
The CPU communicates with memory by first
identifying the address of the location and then
passing this address on the address bus.
This is similar to the fact that a mail carrier needs
an address in order to deliver a letter
The data is transferred between memory and the
CPU along the data bus.

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PIC18xxx Separation of Data and Program Memory

1 KB refers
to1,024 bytes of
memory.
1 MB refers to
1,048,576 bytes of
memory.
1 GB refers to
1,073,741,824
bytes of memory.

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PIC18xxx Data Memory
The PIC18 data memory is implemented as SRAM.
Each location in the data memory is also referred to as a
register or file register.
The PIC18 MCU supports 4096 bytes of data memory.
It requires 12 bits of address to select one of the data
registers.

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PIC18xxx Data Memory
The PIC18 data memory is implemented as SRAM.
Each location in the data memory is also referred to as a
register or file register.
The PIC18 MCU supports 4096 bytes of data memory.
It requires 12 bits of address to select one of the data
registers.

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PIC18xxx Data Memory
The PIC18 data memory is implemented as SRAM.
Each location in the data memory is also referred to as a
register or file register.
The PIC18 MCU supports 4096 bytes of data memory.
It requires 12 bits of address to select one of the data
registers.

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PIC18xxxx general instruction set
Four instruction set each made up of 16 bit word
divided into an opcode.
Opcode specifies the instruction type and one or
more operand and the operation of the instruction
Four categories of instruction
◦ Byte-oriented operation
◦ Bit-oriented operations
◦ Literal operations
◦ Control operations

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Byte-oriented operations
This operation has three operands
◦ File register (‘ f ’)
◦ The destination of the result (‘ d ‘)
◦ Accessed memory (‘ a ‘)
The ‘ f ‘ specify which file register to be used by the
instruction and the result of the operation is placed
in a register specified by ‘ d ‘.
If ‘ d ‘ = 0, result is placed in WREG

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Byte-oriented instruction format

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Byte-oriented
Byte-to-byte operation (two word) instruction
format  MOVFF FL, F2
This allow data to be moved from one register to
another

Example Instruction set

MOVFF MYREG1, MYREG2
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Bit-oriented operation
Made up of three operand
◦ The file register (specified by ‘ f ’)
◦ The bit in the file register (specified by ‘ b ’)
◦ The accessed memory (specified by ‘ a ’)
‘ b ’ selects the number of the bit affected by
the operation, while ‘ f ’ represents the
number of the file in which the bit is located.

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Bit-oriented instruction format

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Control operation
The control instructions may use some of
the following operands:
◦ A program memory address (specified by ‘ n
’)
◦ The mode of the CALL or RETURN
instructions (specified by ‘ s ’
◦ The mode of the table read and table write
instructions (specified by ‘ m ’)
◦ No operand required (specified by ‘—’)
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Addressing mode
MCUs use addressing mode to specify the operand
to be operated on
◦ Register direct
◦ Immediate
◦ Inherent
◦ Indirect
◦ Bit-direct
It defines how machine language instruction in a
particular architecture identify the operand of each
instruction

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Register direct
8-bit value is used to specify a data register as
operand  Access bank or other bank
Access bank: 8-bit value is used to select a register
in the bank,  the bank value in the BSR (bit
set/reset) register is ignored.
Otherwise, the access is completed by memory
bank specified in the BSR register
movwf OxlA, BANKED

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Register direct – example
movwf OxlA, BANKED
◦ copies the contents of the WREG register to the memory
location OxlA in the bank specified by the BSR register.
movwf 0x45, A
◦ copies the contents of the WREG register to the memory
location 0x45 in the access bank A
movff regl, reg2
◦ copies the contents of the register regl to the register
reg2. Both regl and reg2 are 12-bit values  BSR value is
ignored in this case

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Data movement instructions
Data movement instruction is required to place
data in appropriate register before any useful
operation can done.
Data movement instructions

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Data movement instructions

For example, the instruction

movf 0x20, W, A will copy the contents of the data register at
0x20 to the WREG register.
The movff instruction, a 32-bit instruction, can copy a file register in
one bank to a file register in another bank without referring to the BSR
register.
The movlb k instruction sets the bank k as the active bank. The movlw
k instruction places the value k in the WREG register.

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Example
Write a PIC18 instruction (or instruction sequence) to
transfer data from (a) WREG to data register at 0x30, (b)
the data register at 0x30 to the data register at 0x40, (c)
the data register at 0x40 to WREG, and (d) load the value
0x200 into FSR0.
Solution
(a) movwf 0x30,A ; force access bank >
(b) movff 0x30, 0x40 ;
(c) movf 0x40,W,A ; force access bank and copy register
0x40 to WREG
(d) Ifsr FSRO, 0x200 ;load the value 0x200 into FSRO
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ADD Instruction
ADD is a group of instruction that perform addition
operation
Made up of two or three instruction
Third instruction  carry flag in STATUS register as
operand.
Instructions
◦ addwf f, d, ;a add WREG and f
◦ Addwfc f, d, ;a add WREG, carry bit,
and f
◦ addlw k ;add literal k to WREG

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ADD Instruction – Example
Write an instruction to perform the following operations:
(a) Add the content of WREG and that of the data register
at 0x40 (in access bank) and leave the sum in WREG.
(b) Increment the WREG register by 5.
(c) Add the WREG register, the register with the name of
sum, and carry and leave the result in sum, The variable
sum is in access bank.
Solution
(a) Addwf 0x40, W, A
(b) Addlw 5
(c) Addwfc sum, F, A

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SUB instruction
SUB is the generic name of a group of instructions that
perform the subtraction operation.
The SUB instruction may have two or three operands. A
three-operand SUB instruction includes the carry flag in the
STATUS register as one of the operands.
The PIC 18 MCU provides four SUB instructions:
subfwb f, d. a; subtract f from WREG with borrow
subwf f, d, a; subtract WREG from f
subwfb f, d, a; subtract WREG from f with borrow
sublw k ; subtract WREG from literal

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SUB instruction – Example
Write an instruction sequence to subtract 9 from the data registers
located at 0x50-0x53.
Solution: This operation can be implemented by placing 9 in the
WREG register and then executing the subwf f,F,A instruction.
movlw 0x09 ; place 9 in the WREG register
subwf 0x50, F, A ; decrement the contents of the register at 0x50 by
9;
subwf 0x51,F,A ;decrement the contents of the register at 0x51 by 9
subwf 0x52,F,A ;decrement the contents of the register at 0x52 by 9
subwf 0x53,F, A ;decrement the contents of the register at 0x53 by 9

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Subroutine call and stack
Stack implement  First-In-Last-
Out (FILO) data structure
Stack implement requirement
1. A stack pointer that points to the
top (or the byte immediately
above the top) of the stack
2. A block of RAM of adequate size
A stack can grow
PIC18 uses from a low address
toward higher
FSR (File select register) stack addresses or from a
pointer high address toward
Data memory  Data stack lower addresses
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Stack operation
Stack pointer needs to be initialized the stack can
be accessed  lfsr FSR1, 0x500 or
FSR1, 0xE00
Stack performs push and pop (or pull) operations
◦ A push operation places contents of a register into the
stack location pointed by the stack pointer one after the
other
◦ movwf POSTINC1 ;push WREG register on the stack
◦ movff STATUS, POSTINC1 ;push SATUS register onto the
stack

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Stack operation
◦ movwf POSTINC1 ;push WREG register on the stack
◦ movff STATUS, POSTINC1 ;push SATUS register
onto the stack
◦ movff P0STDEC1, STATUS ; get the stack pointer
decremented
◦ movff INDF1, STATUS ; pop the stack onto
STATUS
Set macros for
◦ pushr  to push file register onto the stack
◦ popr  to pop a byte off the stack

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Stack operation
Set macros for
◦ pushr  to push file register onto the stack
◦ popr  to pop a byte off the stack
pushr macro arg ;macro to push the WREG
movff arg, POSTINC!
endm
popr macro arg ;arg is a file register
movff POSTDEC1 ;decrement the stack pointer
movff INDF1, arg ;pop off a byte from the stack onto arg
endm

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Stack operation
To push value onto the stack  a third macro
that use pushr
push_dat macro dat ;this macro push the
value dat onto the stack
movlw dat
pushr WREG
endm

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Stack operation – example
Utilize the macro defined earlier to push the WREG
and STATUS register onto the stack and pop the top
two bytes of the stack onto the data memory
locations at 0x00 and 0x01.
Solution
1. pushing WREG: pushr WREG
2. pushing STATUS: pushr STATUS
3. popping onto 0x00: popr 0x00
4. popping onto 0x01: pop 0x01

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Subroutine call and stack
A subroutine is a sequence of instructions that can be called from many
different places in a program.
Subroutines may also call other subroutines. Programs written in this
manner are called structured programs (structured programming)
Subroutine call mechanism in PIC18
1. The rcall n and call k[,s] instructions for making the subroutine call and
the return instruction for returning from the subroutine
2. A return address stack for saving and restoring return addresses
3. A return stack pointer that points to the top of the return address stack
4. The push and pull instructions for pushing values onto the return
address stack and pulling values from the return address stack
5. A one-layer-deep fast register stack for fast saving and restoring the
STATUS, WREG, and BSR registers during interrupts and subroutine calls
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Subroutine call instructions
PIC18  two instruction for subroutine call
rcall find_max ;calls find_max subroutine, size <= 1 k word
If size > 1 word, call k[, s] is used. This can push STATUS, WREG and
BSR registers onto repective shadow registers
call sq_root, 1 ;call sq_toot subroutine and save BSR,
STATUS and WREG register in the fast register stack (or shadow
register)
The return instruction
return [s]
◦ The return address stack is popped and the top of the stack is load
into the program counter.
◦ Control is transferred back to the caller of the subroutine
◦ Is s = 1, BSR, STATUS and WREG registers are reloaded from the
shadow register 51
Comp. performance enhancement techniques
Typical techniques used to improve computer
performance include:
◦ higher clock frequencies
◦ faster memories and caches
◦ increasing the number of internal registers
◦ multiple buses
◦ simple hardwired instructions
◦ pipelining
◦ super pipelining
◦ multiple functional units that operate in parallel
◦ superscalar operation
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Performance measurement
The performance of a computer system can be
defined in a number of different ways.
The relevant definition depends on the intended
application of the system.
For example, the performance of a workstation
might be measured in terms of the amount of time
it takes to complete a specific job.
Included in this is not only the speed of the CPU,
but also the speed of the memory and I/O systems.

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Performance measurement
the performance of a main frame in a computer
center would most likely be defined in terms of its
throughput, i.e. the number of jobs that it
completes per unit time.
For interactive systems the performance might be
measured in terms of the system response time.
In this case the system with the highest
performance would be the one with the fastest
response time or shortest execution time.

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Performance measurement
Performance and execution time are thus related
by:

if the performance of machine A is greater than

that of machine B, then the execution time for
machine A is shorter than the execution time for
machine B for the same job.

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Performance measurement
Performance and execution time are thus related by:

Suppose that machine A runs a program in 10 seconds while

machine B runs the same program in 15 seconds, then
 

 
Thus, machine A has 1.5 times the performance of machine
B.

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Performance measurement
How to?
Time is the best measure of computer performance:
◦ the computer that performs the same amount of work in the
least time is the fastest.
◦ Elapsed time or wall-clock time is the total time required to
complete a task, including disk accesses, memory accesses, I/O
activities, operating system overhead, etc
CPU time is defined as the time that the CPU actually
spends executing the instructions from a program, not
including the time spent waiting for I/O or spent executing
instructions from other programs in a time sharing system.

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Performance measurement
CPU time is defined as the time that the CPU actually spends
executing the instructions from a program, not including the time
spent waiting for I/O or spent executing instructions from other
programs in a time sharing system.

System performance is often used to refer to

the elapsed time required for a program on
an unloaded system.
CPU performance is used to refer to the time
spent executing user instructions for a
particular program.

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Performance matrics
computers are constructed using a clock that runs at
a constant rate and determines when events take
place in the hardware
These discrete time intervals are called clock cycles
(ticks, clock periods, clocks or cycles)
The length of a clock period is the time
corresponding to a complete clock cycle (e.g., 10
nanoseconds, or 10ns) and the clock rate is the
number of clock cycles per second (e.g., 100
megahertz, or 100 MHz).

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Performance matrics
In CPU performance

Or

Performance can be improved by reducing either

the clock cycle time or the number of CPU clocks
required to execute a program

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Example
Suppose that a program runs in 10 seconds on
computer A, which has a 100 MHz clock. If a
technique is employed to increase the clock rate of
the computer, but the technique causes the
modified computer to require 1.2 times as many
clock cycles as the original machine, what new
clock rate would be needed to yield an execution
time on the modified machine of 6 seconds?

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Solution

CPU clock cycles = 109 cycles

The clock rate required for a 6 second CPU time is
given by

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Solution
The modified machine would therefore require
twice the clock rate to run the program in 6
seconds. Thus doubling the clock rate only yields
1.67 times the original performance.
The number of clock cycles required for a program
depends of course on the number of instructions in
the program.


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Solution
The number of clock cycles required for a program
depends of course on the number of instructions in
the program.

where CPI is the average number of clock cycles per
instruction. Note that

Or
performance can be enhanced by reducing the
instruction count, the CPI or the clock cycle time (i.e.
increasing the clock rate). 64
Chapter 2 – Data representation

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