Bipolar Logic

 Bipolar logic families use semiconductor diodes and bipolar junction transistors as the basic
building blocks of logic circuits.
Diode Logic
 Use diodes and resistors to perform logic operations.
 Logic levels in a simple diode logic system:

o Diode AND gate

 Suppose that both inputs are connected to HIGH voltage.
 Say VA =VB =4 V
 Both diodes are forward biased and Truth table Vout is one diode
drop above 4v.
A B out
Vout=4+0.7=4.7V (High) 0 0 0
 If one of the inputs is LOW- say 1V, then the 0 1 0
output Vout will be one diode drop above the 1 0 0
lower input. The same will be the output if both 1 1 1
the inputs are LOW.
1 Vout=1+0.7=1.7V (LOW)
 o Diode OR gate
 If one of the inputs is HIGH, the output will be one diode drop below the
higher input. (i.e. 4-0.7=3.3V: HIGH)
 If both of the inputs are LOW, then the output LOW. (i.e. one diode drop
below the low value, 1-0.7=0.3V)
Truth table
A B out
0 0 0
0 1 1
1 0 1
1 1 1
Transistor Logic Inverter
 The common-emitter configuration of an npn transistor is shown below as a logic
inverter.

 When VIN is HIGH, the transistor switch is closed, and

the output terminal is connected to ground, definitely a
LOW voltage. When VIN is LOW, the transistor switch
is open and the output terminal is pulled to +5 V
through a resistor; the output voltage is HIGH.
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 Transistor-Transistor Logic
 The most commonly used bipolar logic family is transistor-transistor logic.
 Before the emergence of CMOS, the dominant technology was transistor-
transistor logic, commonly referred to as TTL.
 VIL = 0.8 V and VIH = 2 V. The maximum output voltage produced for logic
0 is VOL = 0.4 V, and the minimum voltage produced for logic 1 is VOH = 2.4
V.

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 The operation of the TTL NAND gate is given in the
following table.

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 Emitter Coupled Logic (ECL)
 The fastest bipolar circuit architecture with much more power consumption.

ECL OR/NOR Gate

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 Description from data sheet

Typical datasheet for 74LS00

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 Voltage Levels in Logic Gates
 Consider the NMOS inverter:

 When Vx = 0 V, the NMOS transistor is turned

off. No current flows; hence Vf = 5 V.
 When Vx = VDD, the NMOS transistor is turned
on. To calculate the value of Vf , let us represent
the NMOS transistor by a resistor with the value
RDS=
 Assuming
and

Vf becomes:

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 The CMOS Inverter
 The meaning of the symbol VOH is the voltage produced when the output is
high and VOL refers to the voltage produced when the output is low.
 For the previous NMOS inverter, and
 Consider the CMOS inverter
 The voltage transfer characteristic

 Due to leakage current, the

value of VOH and VOL will
be affected. Thus, typical
value of VOL is 0.1mV
rather than 0V.

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  From the voltage transfer characteristic:
 The voltage VIL is defined as the maximum input voltage level that the
inverter will interpret as low, hence producing a high output.
 The voltage VIH is the minimum input voltage level that the inverter will
interpret as high, hence producing a low output.
 Noise Margin
 Electronic circuits are constantly subjected to random perturbations,
called noise, which can alter the output voltage levels.
 Consider the two NOT gates shown below,

 The ability to tolerate noise without affecting the correct operation of

the circuit is known as noise margin.
 For the low output voltage, we define the low noise margin as
NML = VIL − VOL
 The high noise margin is defined as
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NMH = VOH − VIH
  Dynamic Operation of Logic Gates
 Consider the connection of two NOT gates with the stray capacitance.

 The existence of stray

capacitance has a
negative effect on the
speed of operation of
logic circuits

 Voltage across a capacitor cannot change instantaneously. In this circuit,

when the PMOS transistor in N1 is turned on, the capacitor is charged to
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VDD; it is discharged when the NMOS transistor is turned on.
In real circuits, waveforms do not have perfectly vertical
edges in transition from one logic level to the other.
For the previous circuit with stray capacitance:

 Where:
tr: Rise
time
tf: fall time

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 Power Dissipation in Logic Gates
Define two types of power:
 Static power: Dissipated by the current that flows in the steady state.
 Dynamic power: Consumed when the current flows because of changes in
signal levels.
 NMOS circuits consume static power as well as dynamic power, while
CMOS circuits consume only dynamic power.
 Consider the CMOS inverter:
 Due to the stray capacitance, current flows through the transistors
during charging and discharging.

 From the voltage transfer

characteristics also, there
is a range of input
voltage Vx during which
both transistors are
turned on and current
flows from VDD to Gnd.
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  Fan-in and Fan-out in Logic Gates
 Fan-in
 The fan-in of a logic gate is defined as the number of inputs to the
gate.
 In some logic gate configuration, it may be impractical to increase
the number of inputs beyond a small number. However; in others,
is practical to build high fan-in.
- propagation delay
- Noise margin
 High fan-in CMOS logic gates always require either k NMOS or k
PMOS transistors in series and are therefore never practical.
 Fan-out
 The number of other gates that a specific gate drives is called its fan-
out.
 The driven gates contributes to the capacitive load, and could affect the
propagation delay.

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 Reading assignment
Chapter 3, Wakerly, Digital Design Principles and
Practices.
Section 3.8 Vranesic, Fundamentals of Digital Logic
With Verilog Design.

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 Exercise:
1) Indicate the equivalent gate
a)

b)

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 Ans 1:
a)

b)

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 2) For the input waveform in figure below, what logic circuit will generate the
output waveform shown?

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 3) Derive the truth table and Boolean expression for the following logic
circuit:

A
A

B
B

C
C

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 4) In a certain chemical-processing plant, a liquid chemical is used in a
manufacturing process. The chemical is stored in three different tanks. A
level sensor in each tank produces a HIGH voltage when the level of
chemical in the tank drops below a specified point. Design a circuit that
monitors the chemical level in each tank and indicates when the level in
any two tanks drops below the specified point.
a) Formulate the truth table
b) Implement the simples sop expression.

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 Q#5) Two large tanks at a chemical plant contains different liquids being
heated. A liquid-level sensor is being used to detect whenever the level in
tank A rises above a predetermined level. Temperature sensor in tank B
detects when the temperature in this tank drops below a prescribed
temperature limit. Assume that the liquid-level sensor output is LOW when
the level is satisfactory and HIGH when the level is too high. Also, the
temperature sensor output is LOW when the temperature is satisfactory and
HIGH when the temperature is too LOW.  Design a simple logic circuit that
will detect whenever the level in tank A is too high at the same time the
temperature in tank B is too low.

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