STATE MACHINE ENCODING

STATE MACHINE ENCODING

y It is a computational model y Implemented using Boolean functions and Flip-Flops.

Combinational logic

Reg

y Two things have to be taken into account for designing State

Machine :
 State Transition Graph  State Machine Synthesis Process

1. State Transition Graph:

Describes state machine in terms of its input and output at that particular state and its transition to the next state.

2. State Machine Synthesis Process:

It generates a gate-level circuit based on machines specifications. It allocates state register and assigns binary codes to represent symbolic states,this process is called Encoding.

 Encoding of state machine determines the quality of the gate-

level circuit in terms of area , power , speed , etc.

To optimize the design, normally minimum number of bits that

are enough to represent all states are used.

Transition Analysis of State Encoding

y Here two parameters are taken into account :
 Expected number of bit transitions.  Expected number of transitions of output signals.

Consider the figures shown below which represent functionally identical state machines M1 and M2 with different encodings.

0.1 0.3 0.4 00 0.1 01 00 0.1 11 0.1 0.3 01

0.1 0.1 0.4 11

 Binary codes within the bubbles represent state encoding .  Labels at the transition edges represent the probabilities that transitions

will occur.
 Sum of all the probability must equal 1.  E[M] represents expected number of state bit transitions and is

given by sum of products of edge probabilities and their associated number of bit flips as given by encoding.

y Expected state transitions of the above figure are given as :

 E[M1] = 2 * 0.3+ 2* 0.4 + 1* 0.1 + 1* 0.1 = 1.6  E[M2] = 1* 0.3 + 1* 0.4 + 1* 0.1 + 2 * 0.1 = 1.0

Machines with lower E[M] are more power efficient because :

1. 2.

Fewer transitions lead to lower power dissipation. Fewer transitions are propagated into combinational logic of machine.

A large state machine dissipates more power because more gates and nodes toggle in the circuit.

Design trade offs in State Machine Encoding

y State encoding affects power dissipation as well as area of the machine.
 Problem 1 : It is very difficult to find the encoding technique that minimizes

the state-bit transition E[M].

 Problem 2 : Logic synthesis system can perform automatic state encoding for

area minimization but it may not be desirable for power dissipation because the expected transition is high.
 Problem 3 : If states are encoded to minimize power dissipation , the area has

to be increased.
 One solution to above problems is to use a subset of states that spans high

probability edges i.e encode the state incident to high probability edges to reduce E[M].

y For example, edges incident to states like reset and interrupt

states of a CPU have very low transition probability whereas states like instruction fetch and memory access have very high probabilities.
y To measure the probabilities of state machine behavioral level

simulation can be used.